aboutsummaryrefslogtreecommitdiff
path: root/hw/gx.c
blob: 31de7b57fb76353fe7977c9ff4f08219c0a75c8e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
/* Copyright 2013-2014 IBM Corp.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * 	http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
 * implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#include <skiboot.h>
#include <gx.h>
#include <xscom.h>

/*
 * Note: This file os only used on P7/P7+
 */

/* Configuration of the PSI BUID, see the explanation in
 * interrupts.h
 */
static int gx_p7_configure_psi_buid(uint32_t chip, uint32_t buid)
{
	uint64_t mode1;
	int rc;

	rc = xscom_read(chip, GX_P7_MODE1_REG, &mode1);
	if (rc) {
		prerror("GX: XSCOM error %d reading GX MODE1 REG\n", rc);
		return rc;
	}

	mode1 = SETFIELD(GX_P7_MODE1_PSI_BUID, mode1, buid);
	mode1 &= ~GX_P7_MODE1_PSI_BUID_DISABLE;

	printf("GX: MODE1_REG set to 0x%llx\n", mode1);
	rc = xscom_write(chip, GX_P7_MODE1_REG, mode1);
	if (rc) {
		prerror("GX: XSCOM error %d writing GX MODE1 REG\n", rc);
		return rc;
	}

	return 0;
}

static int gx_p7p_configure_psi_buid(uint32_t chip, uint32_t buid)
{
	uint64_t mode4;
	int rc;

	rc = xscom_read(chip, GX_P7P_MODE4_REG, &mode4);
	if (rc) {
		prerror("GX: XSCOM error %d reading GX MODE1 REG\n", rc);
		return rc;
	}

	mode4 = SETFIELD(GX_P7P_MODE4_PSI_BUID, mode4, buid);
	mode4 &= ~GX_P7P_MODE4_PSI_BUID_DISABLE;

	rc = xscom_write(chip, GX_P7P_MODE4_REG, mode4);
	if (rc) {
		prerror("GX: XSCOM error %d writing GX MODE1 REG\n", rc);
		return rc;
	}

	return 0;
}

/* Configure the BUID of the PSI interrupt in the GX
 * controller.
 *
 * @chip: Chip number (0..31)
 * @buid: 9-bit BUID value
 */
int gx_configure_psi_buid(uint32_t chip, uint32_t buid)
{
	uint32_t pvr = mfspr(SPR_PVR);

	printf("GX: PSI BUID for PVR %x (type %x) chip %d BUID 0x%x\n",
	       pvr, PVR_TYPE(pvr), chip, buid);
	       
	switch(PVR_TYPE(pvr)) {
	case PVR_TYPE_P7:
		return gx_p7_configure_psi_buid(chip, buid);
	case PVR_TYPE_P7P:
		return gx_p7p_configure_psi_buid(chip, buid);
	}
	return -1;
}


static int gx_p7_configure_tce_bar(uint32_t chip, uint32_t gx, uint64_t addr,
				   uint64_t size)
{
	uint32_t areg, mreg;
	int rc;

	switch (gx) {
	case 0:
		areg = GX_P7_GX0_TCE_BAR;
		mreg = GX_P7_GX0_TCE_MASK;
		break;
	case 1:
		areg = GX_P7_GX1_TCE_BAR;
		mreg = GX_P7_GX1_TCE_MASK;
		break;
	default:
		return -EINVAL;
	}

	if (addr) {
		uint64_t taddr, tmask;

		/* The address field contains bits 18 to 43 of the address */
		taddr = SETFIELD(GX_P7_TCE_BAR_ADDR, 0ul,
				 (addr >> GX_P7_TCE_BAR_ADDR_SHIFT));
		taddr |= GX_P7_TCE_BAR_ENABLE;
		tmask = SETFIELD(GX_P7_TCE_MASK, 0ul,
				 ~((size - 1) >> GX_P7_TCE_BAR_ADDR_SHIFT));
		rc = xscom_write(chip, areg, 0);
		rc |= xscom_write(chip, mreg, tmask);
		rc |= xscom_write(chip, areg, taddr);
	} else {
		rc = xscom_write(chip, areg, 0);
	}
	return rc ? -EIO : 0;
}

/* Configure the TCE BAR of a given GX bus
 *
 * @chip: Chip number (0..31)
 * @gx  : GX bus index
 * @addr: base address of TCE table
 * @size: size of TCE table
 */
int gx_configure_tce_bar(uint32_t chip, uint32_t gx, uint64_t addr,
			 uint64_t size)
{
	uint32_t pvr = mfspr(SPR_PVR);

	printf("GX: TCE BAR for PVR %x (type %x) chip %d gx %d\n",
	       pvr, PVR_TYPE(pvr), chip, gx);

	/* We only support P7... is there a P7+ with P5IOC2 ? */
	switch(PVR_TYPE(pvr)) {
	case PVR_TYPE_P7:
		return gx_p7_configure_tce_bar(chip, gx, addr, size);
	}
	return -EINVAL;
}