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<section id="skiboot-5-9-5">
<span id="id1"></span><h1>skiboot-5.9.5<a class="headerlink" href="#skiboot-5-9-5" title="Permalink to this headline">¶</a></h1>
<p>skiboot 5.9.5 was released on Wednesday December 13th, 2017. It replaces
<a class="reference internal" href="skiboot-5.9.4.html#skiboot-5-9-4"><span class="std std-ref">skiboot-5.9.4</span></a> as the current stable release in the 5.9.x series.</p>
<p>Over <a class="reference internal" href="skiboot-5.9.4.html#skiboot-5-9-4"><span class="std std-ref">skiboot-5.9.4</span></a>, we have a few bug fixes, they are:</p>
<ul>
<li><p>Fix <em>extremely</em> rare race in timer code.</p></li>
<li><p>xive: Ensure VC informational FIRs are masked</p>
<p>Some HostBoot versions leave those as checkstop, they are harmless
and can sometimes occur during normal operations.</p>
</li>
<li><p>xive: Fix occasional VC checkstops in xive_reset</p>
<p>The current workaround for the scrub bug described in
__xive_cache_scrub() has an issue in that it can leave
dirty invalid entries in the cache.</p>
<p>When cleaning up EQs or VPs during reset, if we then
remove the underlying indirect page for these entries,
the XIVE will checkstop when trying to flush them out
of the cache.</p>
<p>This replaces the existing workaround with a new pair of
workarounds for VPs and EQs:</p>
<ul class="simple">
<li><p>The VP one does the dummy watch on another entry than
the one we scrubbed (which does the job of pushing old
stores out) using an entry that is known to be backed by
a permanent indirect page.</p></li>
<li><p>The EQ one switches to a more efficient workaround
which consists of doing a non-side-effect ESB load from
the EQ’s ESe control bits.</p></li>
</ul>
</li>
<li><p>io: Add load_wait() helper</p>
<p>This uses the standard form twi/isync pair to ensure a load
is consumed by the core before continuing. This can be necessary
under some circumstances for example when having the following
sequence:</p>
<ul class="simple">
<li><p>Store reg A</p></li>
<li><p>Load reg A (ensure above store pushed out)</p></li>
<li><p>delay loop</p></li>
<li><p>Store reg A</p></li>
</ul>
<p>IE, a mandatory delay between 2 stores. In theory the first store
is only guaranteed to rach the device after the load from the same
location has completed. However the processor will start executing
the delay loop without waiting for the return value from the load.</p>
<p>This construct enforces that the delay loop isn’t executed until
the load value has been returned.</p>
</li>
<li><p>xive: Do not return a trigger page for an escalation interrupt</p>
<p>This is bogus, we don’t support them. (Thankfully the callers
didn’t actually try to use this on escalation interrupts).</p>
</li>
<li><p>xive: Mark a freed IRQ’s IVE as valid and masked</p>
<p>Removing the valid bit means a FIR will trip if it’s accessed
inadvertently. Under some circumstances, the XIVE will speculatively
access an IVE for a masked interrupt and trip it. So make sure that
freed entries are still marked valid (but masked).</p>
</li>
<li><p>hw/nx: Fix NX BAR assignments</p>
<p>The NX rng BAR is used by each core to source random numbers for the
DARN instruction. Currently we configure each core to use the NX rng of
the chip that it exists on. Unfortunately, the NX can be deconfigured by
hostboot and in this case we need to use the NX of a different chip.</p>
<p>This patch moves the BAR assignments for the NX into the normal nx-rng
init path. This lets us check if the normal (chip local) NX is active
when configuring which NX a core should use so that we can fallback
gracefully.</p>
</li>
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