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<div class="section" id="skiboot-5-9-2">
<span id="id1"></span><h1>skiboot-5.9.2<a class="headerlink" href="#skiboot-5-9-2" title="Permalink to this headline">¶</a></h1>
<p>skiboot 5.9.2 was released on Thursday November 16th, 2017. It replaces
<a class="reference internal" href="skiboot-5.9.1.html#skiboot-5-9-1"><span class="std std-ref">skiboot-5.9.1</span></a> as the current stable release in the 5.9.x series.</p>
<p>Over <a class="reference internal" href="skiboot-5.9.1.html#skiboot-5-9-1"><span class="std std-ref">skiboot-5.9.1</span></a>, we have a few PHB4 (PCI) fixes, an i2c fix for
POWER9 platforms to avoid conflicting with the OCC use and an important
NPU2 (NVLink2) fix.</p>
<ul>
<li><p class="first">phb4: Fix lane equalisation setting</p>
<p>Fix cut and paste from phb3. The sizes have changes now we have GEN4,
so the check here needs to change also</p>
<p>Without this we end up with the default settings (all ‘7’) rather
than what’s in HDAT.</p>
</li>
<li><p class="first">phb4: Fix PE mapping of M32 BAR</p>
<p>The M32 BAR is the PHB4 region used to map all the non-prefetchable
or 32-bit device BARs. It’s supposed to have its segments remapped
via the MDT and Linux relies on that to assign them individual PE#.</p>
<p>However, we weren’t configuring that properly and instead used the
mode where PE# == segment#, thus causing EEH to freeze the wrong
device or PE#.</p>
</li>
<li><p class="first">phb4: Fix lost bit in PE number on config accesses</p>
<p>A PE number can be up to 9 bits, using a uint8_t won’t fly..</p>
<p>That was causing error on config accesses to freeze the
wrong PE.</p>
</li>
<li><p class="first">phb4: Update inits</p>
<p>New init value from HW folks for the fence enable register.</p>
<p>This clears bit 17 (CFG Write Error CA or UR response) and bit 22 (MMIO Write
DAT_ERR Indication) and sets bit 21 (MMIO CFG Pending Error)</p>
</li>
<li><p class="first">npu2: Move to new GPU memory map</p>
<p>There are three different ways we configure the MCD and memory map.</p>
<ol class="arabic simple">
<li>Old way (current way)
Skiboot configures the MCD and puts GPUs at 4TB and below</li>
<li>New way with MCD
Hostboot configures the MCD and skiboot puts GPU at 4TB and above</li>
<li>New way without MCD
No one configures the MCD and skiboot puts GPU at 4TB and below</li>
</ol>
<p>The change keeps option 1 and adds options 2 and 3.</p>
<p>The different configurations are detected using certain scoms (see
patch).</p>
<p>Option 1 will go away eventually as it’s a configuration that can
cause xstops or data integrity problems. We are keeping it around to
support existing hostboot.</p>
<p>Option 2 supports only 4 GPUs and 512GB of memory per socket.</p>
<p>Option 3 supports 6 GPUs and 4TB of memory but may have some
performance impact.</p>
</li>
<li><p class="first">p8-i2c: Don’t write the watermark register at init</p>
<p>On P9 the I2C master is shared with the OCC. Currently the watermark
values are set once at init time which is bad for two reasons:</p>
<ol class="loweralpha simple">
<li>We don’t take the OCC master lock before setting it. Which
may cause issues if the OCC is currently using the master.</li>
<li>The OCC might change the watermark levels and we need to reset
them.</li>
</ol>
<p>Change this so that we set the watermark value when a new transaction
is started rather than at init time.</p>
</li>
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