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<div class="section" id="skiboot-5-9-rc1">
<span id="id1"></span><h1>skiboot-5.9-rc1<a class="headerlink" href="#skiboot-5-9-rc1" title="Permalink to this headline">¶</a></h1>
<p>skiboot v5.9-rc1 was released on Wednesday October 11th 2017. It is the first
release candidate of skiboot 5.9, which will become the new stable release
of skiboot following the 5.8 release, first released August 31st 2017.</p>
<p>skiboot v5.9-rc1 contains all bug fixes as of <a class="reference internal" href="skiboot-5.4.7.html#skiboot-5-4-7"><span class="std std-ref">skiboot-5.4.7</span></a>
and <a class="reference internal" href="skiboot-5.1.21.html#skiboot-5-1-21"><span class="std std-ref">skiboot-5.1.21</span></a> (the currently maintained stable releases). We
do not currently expect to do any 5.8.x stable releases.</p>
<p>For how the skiboot stable releases work, see <a class="reference internal" href="../process/stable-skiboot-rules.html#stable-rules"><span class="std std-ref">Skiboot stable tree rules and releases</span></a> for details.</p>
<p>The current plan is to cut the final 5.9 by October 17th, with skiboot 5.9
being for all POWER8 and POWER9 platforms in op-build v1.20 (Due October 18th).
This release will be targetted to early POWER9 systems.</p>
<p>Over skiboot-5.8, we have the following changes:</p>
<div class="section" id="new-features">
<h2>New Features<a class="headerlink" href="#new-features" title="Permalink to this headline">¶</a></h2>
<div class="section" id="power8">
<h3>POWER8<a class="headerlink" href="#power8" title="Permalink to this headline">¶</a></h3>
<ul>
<li><p class="first">fast-reset by default (if possible)</p>
<p>Currently, this is limited to POWER8 systems.</p>
<p>A normal reboot will, rather than doing a full IPL, go through a
fast reboot procedure. This reduces the “reboot to petitboot” time
from minutes to a handful of seconds.</p>
</li>
</ul>
</div>
<div class="section" id="power9">
<h3>POWER9<a class="headerlink" href="#power9" title="Permalink to this headline">¶</a></h3>
<ul>
<li><p class="first">POWER9 power management during boot</p>
<p>Less power should be consumed during boot.</p>
</li>
<li><p class="first">OPAL_SIGNAL_SYSTEM_RESET for POWER9</p>
<p>This implements OPAL_SIGNAL_SYSTEM_RESET, using scom registers to
quiesce the target thread and raise a system reset exception on it.
It has been tested on DD2 with stop0 ESL=0 and ESL=1 shallow power
saving modes.</p>
<p>DD1 is not implemented because it is sufficiently different as to
make support difficult.</p>
</li>
<li><p class="first">Enable deep idle states for POWER9</p>
<ul>
<li><p class="first">SLW: Add support for p9_stop_api</p>
<p>p9_stop_api’s are used to set SPR state on a core wakeup form a deeper
low power state. p9_stop_api uses low level platform formware and
self-restore microcode to restore the sprs to requested values.</p>
<p>Code is taken from :
<a class="reference external" href="https://github.com/open-power/hostboot/tree/master/src/import/chips/p9/procedures/utils/stopreg">https://github.com/open-power/hostboot/tree/master/src/import/chips/p9/procedures/utils/stopreg</a></p>
</li>
<li><p class="first">SLW: Removing timebase related flags for stop4</p>
<p>When a core enters stop4, it does not loose decrementer and time base.
Hence removing flags OPAL_PM_DEC_STOP and OPAL_PM_TIMEBASE_STOP.</p>
</li>
<li><p class="first">SLW: Allow deep states if homer address is known</p>
<p>Use a common variable has_wakeup_engine instead of has_slw to tell if
the:
- SLW image is populated in case of power8
- CME image is populated in case of power9</p>
<p>Currently we expect CME to be loaded if homer address is known ( except
for simulators)</p>
</li>
<li><p class="first">SLW: Configure self-restore for HRMOR</p>
<p>Make a stop api call using libpore to restore HRMOR register. HRMOR needs
to be cleared so that when thread exits stop, they arrives at linux
system_reset vector (0x100).</p>
</li>
<li><p class="first">SLW: Add opal_slw_set_reg support for power9</p>
<p>This OPAL call is made from Linux to OPAL to configure values in
various SPRs after wakeup from a deep idle state.</p>
</li>
</ul>
</li>
<li><p class="first">PHB4: CAPP recovery</p>
<p>CAPP recovery is initiated when a CAPP Machine Check is detected.
The capp recovery procedure is initiated via a Hypervisor Maintenance
interrupt (HMI).</p>
<p>CAPP Machine Check may arise from either an error that results in a PHB
freeze or from an internal CAPP error with CAPP checkstop FIR action.
An error that causes a PHB freeze will result in the link down signal
being asserted. The system continues running and the CAPP and PSL will
be re-initialized.</p>
<p>This implements CAPP recovery for POWER9 systems</p>
</li>
<li><p class="first">Add <code class="docutils literal notranslate"><span class="pre">wafer-location</span></code> property for POWER9</p>
<p>Extract wafer-location from ECID and add property under xscom node.
- bits 64:71 are the chip x location (7:0)
- bits 72:79 are the chip y location (7:0)</p>
<p>Sample output:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="p">[</span><span class="n">root</span><span class="nd">@wsp</span> <span class="n">xscom</span><span class="nd">@623fc00000000</span><span class="p">]</span><span class="c1"># lsprop ecid</span>
<span class="n">ecid</span> <span class="mi">019</span><span class="n">a00d4</span> <span class="mi">03100718</span> <span class="mi">852</span><span class="n">c0000</span> <span class="mi">00</span><span class="n">fd7911</span>
<span class="p">[</span><span class="n">root</span><span class="nd">@wsp</span> <span class="n">xscom</span><span class="nd">@623fc00000000</span><span class="p">]</span><span class="c1"># lsprop wafer-location</span>
<span class="n">wafer</span><span class="o">-</span><span class="n">location</span> <span class="mi">00000085</span> <span class="mi">0000002</span><span class="n">c</span>
</pre></div>
</div>
</li>
<li><p class="first">Add <code class="docutils literal notranslate"><span class="pre">wafer-id</span></code> property for POWER9</p>
<p>Wafer id is derived from ECID data.
- bits 4:63 are the wafer id ( ten 6 bit fields each containing a code)</p>
<p>Sample output:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="p">[</span><span class="n">root</span><span class="nd">@wsp</span> <span class="n">xscom</span><span class="nd">@623fc00000000</span><span class="p">]</span><span class="c1"># lsprop ecid</span>
<span class="n">ecid</span> <span class="mi">019</span><span class="n">a00d4</span> <span class="mi">03100718</span> <span class="mi">852</span><span class="n">c0000</span> <span class="mi">00</span><span class="n">fd7911</span>
<span class="p">[</span><span class="n">root</span><span class="nd">@wsp</span> <span class="n">xscom</span><span class="nd">@623fc00000000</span><span class="p">]</span><span class="c1"># lsprop wafer-id</span>
<span class="n">wafer</span><span class="o">-</span><span class="nb">id</span> <span class="s2">"6Q0DG340SO"</span>
</pre></div>
</div>
</li>
<li><p class="first">Add <code class="docutils literal notranslate"><span class="pre">ecid</span></code> property under <code class="docutils literal notranslate"><span class="pre">xscom</span></code> node for POWER9.
Sample output:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="p">[</span><span class="n">root</span><span class="nd">@wsp</span> <span class="n">xscom</span><span class="nd">@623fc00000000</span><span class="p">]</span><span class="c1"># lsprop ecid</span>
<span class="n">ecid</span> <span class="mi">019</span><span class="n">a00d4</span> <span class="mi">03100718</span> <span class="mi">852</span><span class="n">c0000</span> <span class="mi">00</span><span class="n">fd7911</span>
</pre></div>
</div>
</li>
<li><p class="first">Add ibm,firmware-versions device tree node</p>
<p>In P8, hostboot provides mini device tree. It contains <code class="docutils literal notranslate"><span class="pre">/ibm,firmware-versions</span></code>
node which has various firmware component version details.</p>
<p>In P9, OPAL is building device tree. This patch adds support to parse VERSION
section of PNOR and create <code class="docutils literal notranslate"><span class="pre">/ibm,firmware-versions</span></code> device tree node.</p>
<p>Sample output:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">/</span><span class="n">sys</span><span class="o">/</span><span class="n">firmware</span><span class="o">/</span><span class="n">devicetree</span><span class="o">/</span><span class="n">base</span><span class="o">/</span><span class="n">ibm</span><span class="p">,</span><span class="n">firmware</span><span class="o">-</span><span class="n">versions</span> <span class="c1"># lsprop .</span>
<span class="n">occ</span> <span class="s2">"6a00709"</span>
<span class="n">skiboot</span> <span class="s2">"v5.7-rc1-p344fb62"</span>
<span class="n">buildroot</span> <span class="s2">"2017.02.2-7-g23118ce"</span>
<span class="n">capp</span><span class="o">-</span><span class="n">ucode</span> <span class="s2">"9c73e9f"</span>
<span class="n">petitboot</span> <span class="s2">"v1.4.3-p98b6d83"</span>
<span class="n">sbe</span> <span class="s2">"02021c6"</span>
<span class="nb">open</span><span class="o">-</span><span class="n">power</span> <span class="s2">"witherspoon-v1.17-128-gf1b53c7-dirty"</span>
<span class="o">....</span>
<span class="o">....</span>
</pre></div>
</div>
</li>
</ul>
</div>
</div>
<div class="section" id="id2">
<h2>POWER9<a class="headerlink" href="#id2" title="Permalink to this headline">¶</a></h2>
<ul>
<li><p class="first">Disable Transactional Memory on Power9 DD 2.1</p>
<p>Update pa_features_p9[] to disable TM (Transactional Memory). On DD 2.1
TM is not usable by Linux without other workarounds, so skiboot must
disable it.</p>
</li>
<li><p class="first">xscom: Do not print error message for ‘chiplet offline’ return values</p>
<p>xscom_read/write operations returns CHIPLET_OFFLINE when chiplet is offline.
Some multicast xscom_read/write requests from HBRT results in xscom operation
on offline chiplet(s) and printing below warnings in OPAL console:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="p">[</span> <span class="mf">135.036327572</span><span class="p">,</span><span class="mi">3</span><span class="p">]</span> <span class="n">XSCOM</span><span class="p">:</span> <span class="n">Read</span> <span class="n">failed</span><span class="p">,</span> <span class="n">ret</span> <span class="o">=</span> <span class="o">-</span><span class="mi">14</span>
<span class="p">[</span> <span class="mf">135.092689829</span><span class="p">,</span><span class="mi">3</span><span class="p">]</span> <span class="n">XSCOM</span><span class="p">:</span> <span class="n">Read</span> <span class="n">failed</span><span class="p">,</span> <span class="n">ret</span> <span class="o">=</span> <span class="o">-</span><span class="mi">14</span>
</pre></div>
</div>
<p>Some SCOM users can deal correctly with this error code (notably opal-prd),
so the error message is (in practice) erroneous.</p>
</li>
<li><p class="first">IMC: Fix the core_imc_event_mask</p>
<p>CORE_IMC_EVENT_MASK is a scom that contains bits to control event sampling for
different machine state for core imc. The current event-mask setting sample
events only on host kernel (hypervisor) and host userspace.</p>
<p>Patch to enable the sampling of events in other machine states (like guest
kernel and guest userspace).</p>
</li>
<li><p class="first">IMC: Update the nest_pmus array with occ/gpe microcode uav updates</p>
<p>OOC/gpe nest microcode maintains the list of individual nest units
supported. Sync the recent updates to the UAV with nest_pmus array.</p>
<p>For reference occ/gpr microcode link for the UAV:
<a class="reference external" href="https://github.com/open-power/occ/blob/master/src/occ_gpe1/gpe1_24x7.h">https://github.com/open-power/occ/blob/master/src/occ_gpe1/gpe1_24x7.h</a></p>
</li>
<li><p class="first">Parse IOSLOT information from HDAT</p>
<p>Add structure definitions that describe the physical PCIe topology of
a system and parse them into the device-tree based PCIe slot
description.</p>
</li>
<li><p class="first">idle: user context state loss flags fix for stop states</p>
<p>The “lite” stop variants with PSSCR[ESL]=PSSCR[EC]=1 do not lose user
context, while the non-lite variants do (ESL: enable state loss).</p>
<p>Some of the POWER9 idle states had these wrong.</p>
</li>
</ul>
<div class="section" id="capi">
<h3>CAPI<a class="headerlink" href="#capi" title="Permalink to this headline">¶</a></h3>
<ul>
<li><p class="first">POWER9 DD2 update</p>
<p>The CAPI initialization sequence has been updated in DD2.
This patch adapts to the changes, retaining compatibility with DD1.
The patch includes some changes to DD1 fix-ups as well.</p>
</li>
<li><p class="first">Load CAPP microcode for POWER9 DD2.0 and DD2.1</p>
</li>
<li><p class="first">capi: Mask Psl Credit timeout error for POWER9</p>
<p>Mask the PSL credit timeout error in CAPP FIR Mask register
bit(46). As per the h/w team this error is now deprecated and shouldn’t
cause any fir-action for P9.</p>
</li>
</ul>
</div>
<div class="section" id="nvlink2">
<h3>NVLINK2<a class="headerlink" href="#nvlink2" title="Permalink to this headline">¶</a></h3>
<p>A notabale change is that we now generate the device tree description of
NVLINK based on the HDAT we get from hostboot. Since Hostboot will generate
HDAT based on VPD, you now <em>MUST</em> have correct VPD programmed or we will
<em>default</em> to a Sequoia layout, which will lead to random problems if you
are not booting a Sequoia Witherspoon planar. In the case of booting with
old VPD and/or Hostboot, we print a <strong>giant scary warning</strong> in order to scare you.</p>
<ul>
<li><p class="first">npu2: Read slot label from the HDAT link node</p>
<p>Binding GPU to emulated NPU PCI devices is done using the slot labels
since the NPU devices do not have a patching slot node we need to
copy the label in here.</p>
</li>
<li><p class="first">npu2: Copy link speed from the npu HDAT node</p>
<p>This needs to be in the PCI device node so the speed of the NVLink
can be passed to the GPU driver.</p>
</li>
<li><p class="first">npu2: hw-procedures: Add settings to PHY_RESET</p>
<p>Set a few new values in the PHY_RESET procedure, as specified by our
updated programming guide documentation.</p>
</li>
<li><p class="first">Parse NVLink information from HDAT</p>
<p>Add the per-chip structures that descibe how the A-Bus/NVLink/OpenCAPI
phy is configured. This generates the <a class="reference external" href="mailto:npu%40xyz">npu<span>@</span>xyz</a> nodes for each chip on
systems that support it.</p>
</li>
<li><p class="first">npu2: Add vendor cap for IRQ testing</p>
<p>Provide a way to test recoverable data link interrupts via a new
vendor capability byte.</p>
</li>
<li><p class="first">npu2: Enable recoverable data link (no-stall) interrupts</p>
<p>Allow the NPU2 to trigger “recoverable data link” interrupts.</p>
</li>
<li><p class="first">npu2: Implement basic FLR (Function Level Reset)</p>
</li>
<li><p class="first">npu2: hw-procedures: Update PHY DC calibration procedure</p>
</li>
<li><p class="first">npu2: hw-procedures: Change rx_pr_phase_step value</p>
</li>
</ul>
</div>
<div class="section" id="xive">
<h3>XIVE<a class="headerlink" href="#xive" title="Permalink to this headline">¶</a></h3>
<ul>
<li><p class="first">xive: Fix opal_xive_dump_tm() to access W2 properly.
The HW only supported limited access sizes.</p>
</li>
<li><p class="first">xive: Make opal_xive_allocate_irq() properly try all chips</p>
<p>When requested via OPAL_XIVE_ANY_CHIP, we need to try all
chips. We first try the current one (on which the caller
sits) and if that fails, we iterate all chips until the
allocation succeeds.</p>
</li>
<li><p class="first">xive: Fix initialization & cleanup of HW thread contexts</p>
<p>Instead of trying to “pull” everything and clear VT (which didn’t
work and caused some FIRs to be set), instead just clear and then
set the PTER thread enable bit. This has the side effect of
completely resetting the corresponding thread context.</p>
<p>This fixes the spurrious XIVE FIRs reported by PRD and fircheck</p>
</li>
<li><p class="first">xive: Add debug option for detecting misrouted IPI in emulation</p>
<p>This is high overhead so we don’t enable it by default even
in debug builds, it’s also a bit messy, but it allowed me to
detect and debug a locking issue earlier so it can be useful.</p>
</li>
<li><p class="first">xive: Increase the interrupt “gap” on debug builds</p>
<p>We normally allocate IPIs from 0x10. Make that 0x1000 on debug
builds to limit the chances of overlapping with Linux interrupt
numbers which makes debugging code that confuses them easier.</p>
<p>Also add a warning in emulation if we get an interrupt in the
queue whose number is below the gap.</p>
</li>
<li><p class="first">xive: Fix locking around cache scrub & watch</p>
<p>Thankfully the missing locking only affects debug code and
init code that doesn’t run concurrently. Also adds a DEBUG
option that checks the lock is properly held.</p>
</li>
<li><p class="first">xive: Workaround HW issue with scrub facility</p>
<p>Without this, we sometimes don’t observe from a CPU the
values written to the ENDs or NVTs via the cache watch.</p>
</li>
<li><p class="first">xive: Add exerciser for cache watch/scrub facility in DEBUG builds</p>
</li>
<li><p class="first">xive: Make assertion in xive_eq_for_target() more informative</p>
</li>
<li><p class="first">xive: Add debug code to check initial cache updates</p>
</li>
<li><p class="first">xive: Ensure pressure relief interrupts are disabled</p>
<p>We don’t use them and we hijack the VP field with their
configuration to store the EQ reference, so make sure the
kernel or guest can’t turn them back on by doing MMIO
writes to ACK#</p>
</li>
<li><p class="first">xive: Don’t try setting the reserved ACK# field in VPs</p>
<p>That doesn’t work, the HW doesn’t implement it in the cache
watch facility anyway.</p>
</li>
<li><p class="first">xive: Remove useless memory barriers in VP/EQ inits</p>
<p>We no longer update “live” memory structures, we use a temporary
copy on the stack and update the actual memory structure using
the cache watch, so those barriers are pointless.</p>
</li>
</ul>
</div>
<div class="section" id="phb4">
<h3>PHB4<a class="headerlink" href="#phb4" title="Permalink to this headline">¶</a></h3>
<ul>
<li><p class="first">phb4: Mask RXE_ARB: DEC Stage Valid Error</p>
<p>Change the inits to mask out the RXE ARB: DEC Stage Valid Error (bit
370. This has been a fatal error but should be informational only.</p>
<p>This update will be in the next version of the phb4 workbook.</p>
</li>
<li><p class="first">phb4: Add additional adapter to retrain whitelist</p>
<p>The single port version of the ConnectX-5 has a different device ID 0x1017.
Updated descriptions to match pciutils database.</p>
</li>
<li><p class="first">PHB4: Default to PCIe GEN3 on POWER9 DD2.00</p>
<p>You can use the NVRAM override for DD2.00 screened parts.</p>
</li>
<li><p class="first">phb4: Retrain link if degraded</p>
<p>On P9 Scale Out (Nimbus) DD2.0 and Scale in (Cumulus) DD1.0 (and
below) the PCIe PHY can lockup causing training issues. This can cause
a degradation in speed or width in ~5% of training cases (depending on
the card). This is fixed in later chip revisions. This issue can also
cause PCIe links to not train at all, but this case is already
handled.</p>
<p>This patch checks if the PCIe link has trained optimally and if not,
does a full PHB reset (to fix the PHY lockup) and retrain.</p>
<p>One complication is some devices are known to train degraded unless
device specific configuration is performed. Because of this, we only
retrain when the device is in a whitelist. All devices in the current
whitelist have been testing on a P9DSU/Boston, ZZ and Witherspoon.</p>
<p>We always gather information on the link and print it in the logs even
if the card is not in the whitelist.</p>
<p>For testing purposes, there’s an nvram to retry all PCIe cards and all
P9 chips when a degraded link is detected. The new option is
‘pci-retry-all=true’ which can be set using:
<cite>nvram -p ibm,skiboot –update-config pci-retry-all=true</cite>.
This option may increase the boot time if used on a badly behaving
card.</p>
</li>
</ul>
</div>
</div>
<div class="section" id="ibm-fsp-platforms">
<h2>IBM FSP platforms<a class="headerlink" href="#ibm-fsp-platforms" title="Permalink to this headline">¶</a></h2>
<ul>
<li><p class="first">FSP/NVRAM: Handle “get vNVRAM statistics” command</p>
<p>FSP sends MBOX command (cmd : 0xEB, subcmd : 0x05, mod : 0x00) to get vNVRAM
statistics. OPAL doesn’t maintain any such statistics. Hence return
FSP_STATUS_INVALID_SUBCMD.</p>
<p>Fixes these messages appearing in the OPAL log:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="p">[</span><span class="mf">16944.384670488</span><span class="p">,</span><span class="mi">3</span><span class="p">]</span> <span class="n">FSP</span><span class="p">:</span> <span class="n">Unhandled</span> <span class="n">message</span> <span class="n">eb0500</span>
<span class="p">[</span><span class="mf">16944.474110465</span><span class="p">,</span><span class="mi">3</span><span class="p">]</span> <span class="n">FSP</span><span class="p">:</span> <span class="n">Unhandled</span> <span class="n">message</span> <span class="n">eb0500</span>
<span class="p">[</span><span class="mf">16945.111280784</span><span class="p">,</span><span class="mi">3</span><span class="p">]</span> <span class="n">FSP</span><span class="p">:</span> <span class="n">Unhandled</span> <span class="n">message</span> <span class="n">eb0500</span>
<span class="p">[</span><span class="mf">16945.293393485</span><span class="p">,</span><span class="mi">3</span><span class="p">]</span> <span class="n">FSP</span><span class="p">:</span> <span class="n">Unhandled</span> <span class="n">message</span> <span class="n">eb0500</span>
</pre></div>
</div>
</li>
<li><p class="first">fsp: Move common prints to trace</p>
<p>These two prints just end up filling the skiboot logs on any machine
that’s been booted for more than a few hours.</p>
<dl class="docutils">
<dt>They have never been useful, so make them trace level. They were: ::</dt>
<dd><p class="first last">SURV: Received heartbeat acknowledge from FSP
SURV: Sending the heartbeat command to FSP</p>
</dd>
</dl>
</li>
</ul>
</div>
<div class="section" id="bmc-based-systems">
<h2>BMC based systems<a class="headerlink" href="#bmc-based-systems" title="Permalink to this headline">¶</a></h2>
<ul>
<li><p class="first">hw/lpc-uart: read from RBR to clear character timeout interrupts</p>
<p>When using the aspeed SUART, we see a condition where the UART sends
continuous character timeout interrupts. This change adds a (heavily
commented) dummy read from the RBR to clear the interrupt condition on
init.</p>
<p>This was observed on p9dsu systems, but likely applies to other systems
using the SUART.</p>
</li>
<li><p class="first">astbmc: Add methods for handing Device Tree based slots
e.g. ones from HDAT on POWER9.</p>
</li>
</ul>
</div>
<div class="section" id="general">
<h2>General<a class="headerlink" href="#general" title="Permalink to this headline">¶</a></h2>
<ul>
<li><p class="first">ipmi: Convert common debug prints to trace</p>
<p>OPAL logs messages for every IPMI request from host. Sometime OPAL console
is filled with only these messages. This path is pretty stable now and
we have enough logs to cover bad path. Hence lets convert these debug
message to trace/info message. Examples are:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="p">[</span> <span class="mf">1356.423958816</span><span class="p">,</span><span class="mi">7</span><span class="p">]</span> <span class="n">opal_ipmi_recv</span><span class="p">(</span><span class="n">cmd</span><span class="p">:</span> <span class="mh">0xf0</span> <span class="n">netfn</span><span class="p">:</span> <span class="mh">0x3b</span> <span class="n">resp_size</span><span class="p">:</span> <span class="mh">0x02</span><span class="p">)</span>
<span class="p">[</span> <span class="mf">1356.430774496</span><span class="p">,</span><span class="mi">7</span><span class="p">]</span> <span class="n">opal_ipmi_send</span><span class="p">(</span><span class="n">cmd</span><span class="p">:</span> <span class="mh">0xf0</span> <span class="n">netfn</span><span class="p">:</span> <span class="mh">0x3a</span> <span class="nb">len</span><span class="p">:</span> <span class="mh">0x3b</span><span class="p">)</span>
<span class="p">[</span> <span class="mf">1356.430797392</span><span class="p">,</span><span class="mi">7</span><span class="p">]</span> <span class="n">BT</span><span class="p">:</span> <span class="n">seq</span> <span class="mh">0x20</span> <span class="n">netfn</span> <span class="mh">0x3a</span> <span class="n">cmd</span> <span class="mh">0xf0</span><span class="p">:</span> <span class="n">Message</span> <span class="n">sent</span> <span class="n">to</span> <span class="n">host</span>
<span class="p">[</span> <span class="mf">1356.431668496</span><span class="p">,</span><span class="mi">7</span><span class="p">]</span> <span class="n">BT</span><span class="p">:</span> <span class="n">seq</span> <span class="mh">0x20</span> <span class="n">netfn</span> <span class="mh">0x3a</span> <span class="n">cmd</span> <span class="mh">0xf0</span><span class="p">:</span> <span class="n">IPMI</span> <span class="n">MSG</span> <span class="n">done</span>
</pre></div>
</div>
</li>
<li><p class="first">libflash/file: Handle short read()s and write()s correctly</p>
<p>Currently we don’t move the buffer along for a short read() or write()
and nor do we request only the remaining amount.</p>
</li>
<li><p class="first">hw/p8-i2c: Rework timeout handling</p>
<p>Currently we treat a timeout as a hard failure and will automatically
fail any transations that hit their timeout. This results in
unnecessarily failing I2C requests if interrupts are dropped, etc.
Although these are bad things that we should log we can handle them
better by checking the actual hardware status and completing the
transation if there are no real errors. This patch reworks the timeout
handling to check the status and continue the transaction if it can.
if it can while logging an error if it detects a timeout due to a
dropped interrupt.</p>
</li>
<li><p class="first">core/flash: Only expect ELF header for BOOTKERNEL partition flash resource</p>
<p>When loading a flash resource which isn’t signed (secure and trusted
boot) and which doesn’t have a subpartition, we assume it’s the
BOOTKERNEL since previously this was the only such resource. Thus we
also assumed it had an ELF header which we parsed to get the size of the
partition rather than trusting the actual_size field in the FFS header.
A previous commit (9727fe3 DT: Add ibm,firmware-versions node) added the
version resource which isn’t signed and also doesn’t have a subpartition,
thus we expect it to have an ELF header. It doesn’t so we print the
error message “FLASH: Invalid ELF header part VERSION”.</p>
<p>It is a fluke that this works currently since we load the secure boot
header unconditionally and this happen to be the same size as the
version partition. We also don’t update the return code on error so
happen to return OPAL_SUCCESS.</p>
<p>To make this explicitly correct; only check for an ELF header if we are
loading the BOOTKERNEL resource, otherwise use the partition size from
the FFS header. Also set the return code on error so we don’t
erroneously return OPAL_SUCCESS. Add a check that the resource will fit
in the supplied buffer to prevent buffer overrun.</p>
</li>
<li><p class="first">flash: Support adding the no-erase property to flash</p>
<p>The mbox protocol explicitly states that an erase is not required
before a write. This means that issuing an erase from userspace,
through the mtd device, and back returns a successful operation
that does nothing. Unfortunately, this makes userspace tools unhappy.
Linux MTD devices support the MTD_NO_ERASE flag which conveys that
writes do not require erases on the underlying flash devices. We
should set this property on all of our
devices which do not require erases to be performed.</p>
<p>NOTE: This still requires a linux kernel component to set the
MTD_NO_ERASE flag from the device tree property.</p>
</li>
</ul>
</div>
<div class="section" id="utilities">
<h2>Utilities<a class="headerlink" href="#utilities" title="Permalink to this headline">¶</a></h2>
<ul>
<li><p class="first">external/gard: Clear entire guard partition instead of entry by entry</p>
<p>When using the current implementation of the gard tool to ecc clear the
entire GUARD partition it is done one gard record at a time. While this
may be ok when accessing the actual flash this is very slow when done
from the host over the mbox protocol (on the order of 4 minutes) because
the bmc side is required to do many read, erase, writes under the hood.</p>
<p>Fix this by rewriting the gard tool reset_partition() function. Now we
allocate all the erased guard entries and (if required) apply ecc to the
entire buffer. Then we can do one big erase and write of the entire
partition. This reduces the time to clear the guard partition to on the
order of 4 seconds.</p>
</li>
<li><p class="first">opal-prd: Fix opal-prd command line options</p>
<p>HBRT OCC reset interface depends on service processor type.</p>
<ul class="simple">
<li>FSP: reset_pm_complex()</li>
<li>BMC: process_occ_reset()</li>
</ul>
<p>We have both <cite>occ</cite> and <cite>pm-complex</cite> command line interfaces.
This patch adds support to dispaly appropriate message depending
on system type.</p>
<table border="1" class="docutils">
<colgroup>
<col width="6%" />
<col width="39%" />
<col width="55%" />
</colgroup>
<thead valign="bottom">
<tr class="row-odd"><th class="head">SP</th>
<th class="head">Command</th>
<th class="head">Action</th>
</tr>
</thead>
<tbody valign="top">
<tr class="row-even"><td>FSP</td>
<td>opal-prd occ</td>
<td>display error message</td>
</tr>
<tr class="row-odd"><td>FSP</td>
<td>opal-prd pm-complex</td>
<td>Call pm_complex_reset()</td>
</tr>
<tr class="row-even"><td>BMC</td>
<td>opal-prd occ</td>
<td>Call process_occ_reset()</td>
</tr>
<tr class="row-odd"><td>BMC</td>
<td>opal-prd pm-complex</td>
<td>display error message</td>
</tr>
</tbody>
</table>
</li>
<li><p class="first">opal-prd: detect service processor type and
then make appropriate occ reset call.</p>
</li>
<li><p class="first">pflash: Fix erase command for unaligned start address</p>
<p>The erase_range() function handles erasing the flash for a given start
address and length, and can handle an unaligned start address and
length. However in the unaligned start address case we are incorrectly
calculating the remaining size which can lead to incomplete erases.</p>
<p>If we’re going to update the remaining size based on what the start
address was then we probably want to do that before we overide the
origin start address. So rearrange the code so that this is indeed the
case.</p>
</li>
<li><p class="first">external/gard: Print an error if run on an FSP system</p>
</li>
</ul>
</div>
<div class="section" id="simulators">
<h2>Simulators<a class="headerlink" href="#simulators" title="Permalink to this headline">¶</a></h2>
<ul>
<li><p class="first">mambo: Add mambo socket program</p>
<p>This adds a program that can be run inside a mambo simulator in linux
userspace which enables TCP sockets to be proxied in and out of the
simulator to the host.</p>
<p>Unlike mambo bogusnet, it’s requires no linux or skiboot specific
drivers/infrastructure to run.</p>
<p>Run inside the simulator:</p>
<ul class="simple">
<li>to forward host ssh connections to sim ssh server:
<code class="docutils literal notranslate"><span class="pre">./mambo-socket-proxy</span> <span class="pre">-h</span> <span class="pre">10022</span> <span class="pre">-s</span> <span class="pre">22</span></code>, then connect to port 10022
on your host with <code class="docutils literal notranslate"><span class="pre">ssh</span> <span class="pre">-p</span> <span class="pre">10022</span> <span class="pre">localhost</span></code></li>
<li>to allow http proxy access from inside the sim to local http proxy:
<code class="docutils literal notranslate"><span class="pre">./mambo-socket-proxy</span> <span class="pre">-b</span> <span class="pre">proxy.mynetwork</span> <span class="pre">-h</span> <span class="pre">3128</span> <span class="pre">-s</span> <span class="pre">3128</span></code></li>
</ul>
<p>Multiple connections are supported.</p>
</li>
<li><p class="first">idle: disable stop*_lite POWER9 idle states for Mambo platform</p>
<p>Mambo prior to Mambo.7.8.21 had a bug where the stop idle instruction
with PSSCR[ESL]=PSSCR[EC]=0 would resume with MSR set as though it had
taken a system reset interrupt.</p>
<p>Linux currently executes this instruction with MSR already set that
way, so the problem went unnoticed. A proposed patch to Linux changes
that, and causes the idle code to crash. Work around this by disabling
lite stop states for the mambo platform for now.</p>
</li>
</ul>
</div>
</div>
</div>
</div>
</div>
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<h3><a href="../index.html">Table of Contents</a></h3>
<ul>
<li><a class="reference internal" href="#">skiboot-5.9-rc1</a><ul>
<li><a class="reference internal" href="#new-features">New Features</a><ul>
<li><a class="reference internal" href="#power8">POWER8</a></li>
<li><a class="reference internal" href="#power9">POWER9</a></li>
</ul>
</li>
<li><a class="reference internal" href="#id2">POWER9</a><ul>
<li><a class="reference internal" href="#capi">CAPI</a></li>
<li><a class="reference internal" href="#nvlink2">NVLINK2</a></li>
<li><a class="reference internal" href="#xive">XIVE</a></li>
<li><a class="reference internal" href="#phb4">PHB4</a></li>
</ul>
</li>
<li><a class="reference internal" href="#ibm-fsp-platforms">IBM FSP platforms</a></li>
<li><a class="reference internal" href="#bmc-based-systems">BMC based systems</a></li>
<li><a class="reference internal" href="#general">General</a></li>
<li><a class="reference internal" href="#utilities">Utilities</a></li>
<li><a class="reference internal" href="#simulators">Simulators</a></li>
</ul>
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