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  <section id="opal-set-xive">
<span id="id1"></span><h1>OPAL_SET_XIVE<a class="headerlink" href="#opal-set-xive" title="Permalink to this headline">¶</a></h1>
<div class="highlight-c notranslate"><div class="highlight"><pre><span></span><span class="cp">#define OPAL_SET_XIVE                                19</span>

<span class="kt">int64_t</span><span class="w"> </span><span class="nf">opal_set_xive</span><span class="p">(</span><span class="kt">uint32_t</span><span class="w"> </span><span class="n">isn</span><span class="p">,</span><span class="w"> </span><span class="kt">uint16_t</span><span class="w"> </span><span class="n">server</span><span class="p">,</span><span class="w"> </span><span class="kt">uint8_t</span><span class="w"> </span><span class="n">priority</span><span class="p">);</span><span class="w"></span>
</pre></div>
</div>
<p>The host calls this function to set the server (target processor)
and priority parameters of an interrupt source.</p>
<p>This can be also used to mask or unmask the interrupt (by changing
the priority to 0xff one masks an interrupt).</p>
<p>WARNINGS:</p>
<blockquote>
<div><ul class="simple">
<li><p>For MSIs or generally edge sensitive interrupts, OPAL provides no
guarantee as to whether the interrupt will be latched if it occurs
while masked and replayed on unmask. It may or may not. The OS needs
to be aware of this. The current implementation will <em>not</em> replay,
neither on P8 nor on P9 XICS emulation.</p></li>
<li><p>When masking, there is no guarantee that the interrupt will not
still occur after this call returns. The reason is that it might
already be on its way past the source controller and latched into one
of the presenters. There is however a guarantee that it won’t replay
indefinitely so it’s acceptable for the OS to simply ignore it.</p></li>
</ul>
</div></blockquote>
<section id="parameters">
<h2>Parameters<a class="headerlink" href="#parameters" title="Permalink to this headline">¶</a></h2>
<dl class="simple">
<dt><code class="docutils literal notranslate"><span class="pre">isn</span></code></dt><dd><p>This is a global interrupt number as obtained from the device-tree
“interrupts” or “interrupt-map” properties.</p>
</dd>
<dt><code class="docutils literal notranslate"><span class="pre">server_number</span></code></dt><dd><p>is the mangled server (processor) that is to receive the
interrupt request. The mangling means that the actual processor
number is shifted left by 2 bits, the bottom bits representing
the “link”. However links aren’t supported in OPAL so the bottom
2 bits should be 0.</p>
</dd>
<dt><code class="docutils literal notranslate"><span class="pre">priority</span></code></dt><dd><p>is the interrupt priority value applied to the interrupt
(0=highest, 0xFF = lowest/disabled).</p>
</dd>
</dl>
</section>
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