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<div class="section" id="ibm-opal-power-mgt-device-tree-entries">
<span id="power-mgt-devtree"></span><h1>ibm,opal/power-mgt device tree entries<a class="headerlink" href="#ibm-opal-power-mgt-device-tree-entries" title="Permalink to this headline">¶</a></h1>
<div class="toctree-wrapper compound">
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<li class="toctree-l1"><a class="reference internal" href="power-mgt/occ.html">ibm,opal/power-mgt/occ device tree entries</a><ul>
<li class="toctree-l2"><a class="reference internal" href="power-mgt/occ.html#ibm-chip-id">ibm,chip-id</a></li>
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<li class="toctree-l2"><a class="reference internal" href="power-mgt/occ.html#ibm-pstate-vcss-ibm-pstate-vdds">ibm,pstate-vcss ibm,pstate-vdds</a></li>
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</div>
<p>All available CPU idle states are listed in ibm,cpu-idle-state-names</p>
<p>For example:</p>
<div class="highlight-dts notranslate"><div class="highlight"><pre><span></span><span class="nc">power-mgt</span> <span class="p">{</span>
<span class="nf">ibm,cpu-idle-state-names</span> <span class="o">=</span> <span class="s">"nap", "fastsleep_", "winkle"</span><span class="p">;</span>
<span class="nf">ibm,cpu-idle-state-residency-ns</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x1</span> <span class="mh">0x2</span> <span class="mh">0x3</span><span class="p">>;</span>
<span class="nf">ibm,cpu-idle-state-latencies-ns</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x1</span> <span class="mh">0x2</span> <span class="mh">0x3</span><span class="p">>;</span>
<span class="p">};</span>
</pre></div>
</div>
<p>The idle states are characterized by latency and residency
numbers which determine the breakeven point for entry into them. The
latency is a measure of the exit overhead from the idle state and
residency is the minimum amount of time that a CPU must be predicted
to be idle so as to reap the powersavings from entering into that idle
state.</p>
<p>These numbers are made use of by the cpuidle governors in the kernel to
arrive at the appropriate idle state that a CPU must enter into when there is
no work to be done. The values in ibm,cpu-idle-state-latencies-ns are the
the measured latency numbers for the idle states. The residency numbers have
been arrived at experimentally after ensuring that the performance of latency
sensitive workloads do not regress while allowing deeper idle states to be
entered into during low load situations. The kernel is expected to use these
values for optimal power efficiency.</p>
<p>Example:</p>
<div class="highlight-dts notranslate"><div class="highlight"><pre><span></span><span class="k">/</span> <span class="p">{</span>
<span class="nc">ibm,opal</span> <span class="p">{</span>
<span class="nc">power-mgt</span> <span class="p">{</span>
<span class="nf">ibm,pstate-frequencies-mhz</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0xda3</span> <span class="mh">0xd82</span> <span class="mh">0xd60</span> <span class="mh">0xd3f</span> <span class="mh">0xd1e</span> <span class="mh">0xcfd</span> <span class="mh">0xcdb</span> <span class="mh">0xcba</span> <span class="mh">0xc99</span> <span class="mh">0xc78</span> <span class="mh">0xc56</span> <span class="mh">0xc35</span> <span class="mh">0xc14</span> <span class="mh">0xbf3</span> <span class="mh">0xbd1</span> <span class="mh">0xbb0</span> <span class="mh">0xb8f</span> <span class="mh">0xb6e</span> <span class="mh">0xb4c</span> <span class="mh">0xb2b</span> <span class="mh">0xb0a</span> <span class="mh">0xae9</span> <span class="mh">0xac7</span> <span class="mh">0xaa6</span> <span class="mh">0xa85</span> <span class="mh">0xa64</span> <span class="mh">0xa42</span> <span class="mh">0xa21</span> <span class="mh">0xa00</span> <span class="mh">0x9df</span> <span class="mh">0x9bd</span> <span class="mh">0x99c</span> <span class="mh">0x97b</span> <span class="mh">0x95a</span> <span class="mh">0x938</span> <span class="mh">0x917</span> <span class="mh">0x8f6</span> <span class="mh">0x8d5</span> <span class="mh">0x8b3</span> <span class="mh">0x892</span> <span class="mh">0x871</span> <span class="mh">0x850</span> <span class="mh">0x82e</span> <span class="mh">0x80d</span><span class="p">>;</span>
<span class="nf">ibm,cpu-idle-state-latencies-ns</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0xfa0</span> <span class="mh">0x9c40</span> <span class="mh">0x989680</span><span class="p">>;</span>
<span class="nf">ibm,cpu-idle-state-flags</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x11000</span> <span class="mh">0x81003</span> <span class="mh">0x47003</span><span class="p">>;</span>
<span class="nf">ibm,cpu-idle-state-names</span> <span class="o">=</span> <span class="s">"nap", "fastsleep_", "winkle"</span><span class="p">;</span>
<span class="nf">ibm,cpu-idle-state-pmicr</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span> <span class="mh">0x0</span> <span class="mh">0x20</span> <span class="mh">0x0</span> <span class="mh">0x0</span> <span class="mh">0x0</span><span class="p">>;</span>
<span class="nf">ibm,pstate-nominal</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0xffffffef</span><span class="p">>;</span>
<span class="nf">ibm,cpu-idle-state-residency-ns</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x186a0</span> <span class="mh">0x11e1a300</span> <span class="mh">0x3b9aca00</span><span class="p">>;</span>
<span class="nf">ibm,cpu-idle-state-pmicr-mask</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span> <span class="mh">0x0</span> <span class="mh">0x30</span> <span class="mh">0x0</span> <span class="mh">0x0</span> <span class="mh">0x0</span><span class="p">>;</span>
<span class="nf">phandle</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x100002a0</span><span class="p">>;</span>
<span class="nf">ibm,pstate-ids</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span> <span class="mh">0xffffffff</span> <span class="mh">0xfffffffe</span> <span class="mh">0xfffffffd</span> <span class="mh">0xfffffffc</span> <span class="mh">0xfffffffb</span> <span class="mh">0xfffffffa</span> <span class="mh">0xfffffff9</span> <span class="mh">0xfffffff8</span> <span class="mh">0xfffffff7</span> <span class="mh">0xfffffff6</span> <span class="mh">0xfffffff5</span> <span class="mh">0xfffffff4</span> <span class="mh">0xfffffff3</span> <span class="mh">0xfffffff2</span> <span class="mh">0xfffffff1</span> <span class="mh">0xfffffff0</span> <span class="mh">0xffffffef</span> <span class="mh">0xffffffee</span> <span class="mh">0xffffffed</span> <span class="mh">0xffffffec</span> <span class="mh">0xffffffeb</span> <span class="mh">0xffffffea</span> <span class="mh">0xffffffe9</span> <span class="mh">0xffffffe8</span> <span class="mh">0xffffffe7</span> <span class="mh">0xffffffe6</span> <span class="mh">0xffffffe5</span> <span class="mh">0xffffffe4</span> <span class="mh">0xffffffe3</span> <span class="mh">0xffffffe2</span> <span class="mh">0xffffffe1</span> <span class="mh">0xffffffe0</span> <span class="mh">0xffffffdf</span> <span class="mh">0xffffffde</span> <span class="mh">0xffffffdd</span> <span class="mh">0xffffffdc</span> <span class="mh">0xffffffdb</span> <span class="mh">0xffffffda</span> <span class="mh">0xffffffd9</span> <span class="mh">0xffffffd8</span> <span class="mh">0xffffffd7</span> <span class="mh">0xffffffd6</span> <span class="mh">0xffffffd5</span><span class="p">>;</span>
<span class="nf">ibm,pstate-max</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span><span class="p">>;</span>
<span class="nf">ibm,pstate-min</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0xffffffd5</span><span class="p">>;</span>
<span class="p">};</span>
<span class="p">};</span>
<span class="p">};</span>
</pre></div>
</div>
<div class="section" id="ibm-cpu-idle-state-pmicr-ibm-cpu-idle-state-pmicr-mask">
<h2>ibm,cpu-idle-state-pmicr ibm,cpu-idle-state-pmicr-mask<a class="headerlink" href="#ibm-cpu-idle-state-pmicr-ibm-cpu-idle-state-pmicr-mask" title="Permalink to this headline">¶</a></h2>
<p>In POWER8, idle states sleep and winkle have 2 modes- fast and deep. In fast
mode, idle state puts the core into threshold voltage whereas deep mode
completely turns off the core. Choosing fast vs deep mode for an idle state
can be done either via PM_GP1 scom or by writing to PMICR special register.
If using the PMICR path to choose fast/deep mode then ibm,cpu-idle-state-pmicr
and ibm,cpu-idle-state-pmicr-mask properties expose relevant PMICR bits and
values for corresponding idle states.</p>
</div>
<div class="section" id="ibm-cpu-idle-state-psscr-ibm-cpu-idle-state-psscr-mask">
<h2>ibm,cpu-idle-state-psscr ibm,cpu-idle-state-psscr-mask<a class="headerlink" href="#ibm-cpu-idle-state-psscr-ibm-cpu-idle-state-psscr-mask" title="Permalink to this headline">¶</a></h2>
<p>In POWER ISA v3, there is a common instruction ‘stop’ to enter any idle state
and SPR PSSCR is used to specify which idle state needs to be entered upon
executing stop instruction. Properties ibm,cpu-idle-state-psscr and
ibm,cpu-idle-state-psscr-mask expose the relevant PSSCR bits and values for
corresponding idle states.</p>
</div>
<div class="section" id="ibm-cpu-idle-state-flags">
<h2>ibm,cpu-idle-state-flags<a class="headerlink" href="#ibm-cpu-idle-state-flags" title="Permalink to this headline">¶</a></h2>
<p>These flags are used to describe the characteristics of the idle states like
the kind of core state loss caused. These flags are used by the kernel to
save/restore appropriate context while using the idle states.</p>
</div>
<div class="section" id="ibm-pstate-ids">
<h2>ibm,pstate-ids<a class="headerlink" href="#ibm-pstate-ids" title="Permalink to this headline">¶</a></h2>
<p>This property lists the available pstate identifiers, as signed 32-bit
big-endian values. While the identifiers are somewhat arbitrary, these define
the order of the pstates in other ibm,pstate-* properties.</p>
</div>
<div class="section" id="ibm-pstate-frequencies-mhz">
<h2>ibm,pstate-frequencies-mhz<a class="headerlink" href="#ibm-pstate-frequencies-mhz" title="Permalink to this headline">¶</a></h2>
<p>This property lists the frequency, in MHz, of each of the pstates listed in the
ibm,pstate-ids file. Each frequency is a 32-bit big-endian word.</p>
</div>
<div class="section" id="ibm-pstate-max-ibm-pstate-min-ibm-pstate-nominal">
<h2>ibm,pstate-max ibm,pstate-min ibm,pstate-nominal<a class="headerlink" href="#ibm-pstate-max-ibm-pstate-min-ibm-pstate-nominal" title="Permalink to this headline">¶</a></h2>
<p>These properties give the maximum, minimum and nominal pstate values, as an id
specified in the ibm,pstate-ids file.</p>
</div>
<div class="section" id="ibm-pstate-ultra-turbo-ibm-pstate-turbo">
<h2>ibm,pstate-ultra-turbo ibm,pstate-turbo<a class="headerlink" href="#ibm-pstate-ultra-turbo-ibm-pstate-turbo" title="Permalink to this headline">¶</a></h2>
<p>These properties are added when ultra-turbo(WOF) is enabled. These properties
give the max turbo and max ultra-turbo pstate-id as specified in the
ibm,pstate-ids file. The frequencies present in turbo to ultra-turbo range are
referred to as boost/WOF frequencies and these are attained by the CPU under
favourable environmental conditions, low workloads and low active core counts.</p>
<p>Example:</p>
<div class="highlight-dts notranslate"><div class="highlight"><pre><span></span><span class="nc">power-mgt</span> <span class="p">{</span>
<span class="nf">ibm,pstate-core-max</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span> <span class="mh">0x0</span> <span class="mh">0x0</span> <span class="mh">0x0</span> <span class="mh">0x0</span> <span class="mh">0x0</span> <span class="mh">0x0</span><span class="p">>;</span>
<span class="nf">ibm,pstate-turbo</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0xfffffffb</span><span class="p">></span>
<span class="err">ibm</span><span class="p">,</span><span class="err">pstate-ultra-turbo</span> <span class="err">=</span> <span class="p"><</span><span class="mh">0x0</span><span class="p">>;</span>
<span class="p">};</span>
</pre></div>
</div>
</div>
<div class="section" id="ibm-pstate-core-max">
<h2>ibm,pstate-core-max<a class="headerlink" href="#ibm-pstate-core-max" title="Permalink to this headline">¶</a></h2>
<p>This property is added when ultra_turbo(WOF) is enabled. This property gives
the list of max pstate for each ‘n’ number of active cores in the chip.</p>
</div>
<div class="section" id="ibm-pstate-base">
<h2>ibm,pstate-base<a class="headerlink" href="#ibm-pstate-base" title="Permalink to this headline">¶</a></h2>
<p>This pstate points to the base frequency of the chip. POWER9 base frequency is
the highest frequency that is guaranteed when ALL cores are active in ANY
operating condition (ie. workloads, environmental conditions such as max
ambient temperature, active core counts)</p>
</div>
</div>
</div>
</div>
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<div class="sphinxsidebarwrapper">
<h3><a href="../../index.html">Table of Contents</a></h3>
<ul>
<li><a class="reference internal" href="#">ibm,opal/power-mgt device tree entries</a><ul>
<li><a class="reference internal" href="#ibm-cpu-idle-state-pmicr-ibm-cpu-idle-state-pmicr-mask">ibm,cpu-idle-state-pmicr ibm,cpu-idle-state-pmicr-mask</a></li>
<li><a class="reference internal" href="#ibm-cpu-idle-state-psscr-ibm-cpu-idle-state-psscr-mask">ibm,cpu-idle-state-psscr ibm,cpu-idle-state-psscr-mask</a></li>
<li><a class="reference internal" href="#ibm-cpu-idle-state-flags">ibm,cpu-idle-state-flags</a></li>
<li><a class="reference internal" href="#ibm-pstate-ids">ibm,pstate-ids</a></li>
<li><a class="reference internal" href="#ibm-pstate-frequencies-mhz">ibm,pstate-frequencies-mhz</a></li>
<li><a class="reference internal" href="#ibm-pstate-max-ibm-pstate-min-ibm-pstate-nominal">ibm,pstate-max ibm,pstate-min ibm,pstate-nominal</a></li>
<li><a class="reference internal" href="#ibm-pstate-ultra-turbo-ibm-pstate-turbo">ibm,pstate-ultra-turbo ibm,pstate-turbo</a></li>
<li><a class="reference internal" href="#ibm-pstate-core-max">ibm,pstate-core-max</a></li>
<li><a class="reference internal" href="#ibm-pstate-base">ibm,pstate-base</a></li>
</ul>
</li>
</ul>
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