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<section id="device-tree">
<span id="id1"></span><h1>Device Tree<a class="headerlink" href="#device-tree" title="Permalink to this headline">¶</a></h1>
<p>General notes on the Device Tree produced by skiboot. This chapter
<strong>needs updating</strong>.</p>
<section id="general-comments">
<h2>General comments<a class="headerlink" href="#general-comments" title="Permalink to this headline">¶</a></h2>
<ul class="simple">
<li><p>skiboot does not require nodes to have phandle properties, but
if you have them then <em>all</em> nodes must have them including the
root of the device-tree (currently a HB bug !). It is recommended
to have them since they are needed to represent the cache levels.</p></li>
<li><p><strong>NOTE</strong>: The example tree below only has phandle properties for
nodes that are referenced by other nodes. This is <em>not</em> correct
and is purely done for keeping this document smaller, make sure
to follow the rule above.</p></li>
<li><p>Only the “phandle” property is required. Sapphire also generates
a “linux,phandle” for backward compatibility but doesn’t require
it as an input</p></li>
<li><p>Any property not specifically documented must be put in “as is”</p></li>
<li><p>All ibm,chip-id properties contain a HW chip ID which correspond
on P8 to the PIR value shifted right by 7 bits, ie. it’s a 6-bit
value made of a 3-bit node number and a 3-bit chip number.</p></li>
<li><p>Unit addresses (@xxxx part of node names) should if possible use
lower case hexadecimal to be consistent with what skiboot does
and to help some stupid parsers out there…</p></li>
</ul>
</section>
<section id="reserve-map">
<h2>Reserve Map<a class="headerlink" href="#reserve-map" title="Permalink to this headline">¶</a></h2>
<p>Here are the reserve map entries. They should exactly match the
reserved-ranges property of the root node (see documentation
of that property)</p>
<div class="highlight-dts notranslate"><div class="highlight"><pre><span></span><span class="k">/dts-v1/;</span>
<span class="k">/memreserve/</span> <span class="mh">0x00000007fe600000</span> <span class="mh">0x0000000000100000</span><span class="p">;</span>
<span class="k">/memreserve/</span> <span class="mh">0x00000007fe200000</span> <span class="mh">0x0000000000100000</span><span class="p">;</span>
<span class="k">/memreserve/</span> <span class="mh">0x0000000031e00000</span> <span class="mh">0x00000000003e0000</span><span class="p">;</span>
<span class="k">/memreserve/</span> <span class="mh">0x0000000031000000</span> <span class="mh">0x0000000000e00000</span><span class="p">;</span>
<span class="k">/memreserve/</span> <span class="mh">0x0000000030400000</span> <span class="mh">0x0000000000c00000</span><span class="p">;</span>
<span class="k">/memreserve/</span> <span class="mh">0x0000000030000000</span> <span class="mh">0x0000000000400000</span><span class="p">;</span>
<span class="k">/memreserve/</span> <span class="mh">0x0000000400000000</span> <span class="mh">0x0000000000600450</span><span class="p">;</span>
</pre></div>
</div>
</section>
<section id="root-node">
<h2>Root Node<a class="headerlink" href="#root-node" title="Permalink to this headline">¶</a></h2>
<p>Root node of device tree. There are a few required and a few optional properties
that sit in the root node. They’re described here.</p>
<section id="compatible">
<h3>compatible<a class="headerlink" href="#compatible" title="Permalink to this headline">¶</a></h3>
<p>The “compatible” properties are string lists indicating the overall
compatibility from the more specific to the least specific.</p>
<p>The root node compatible property <em>must</em> contain “ibm,powernv” for
Linux to have the powernv platform match the machine.</p>
<p>Each distinct platform <em>MUST</em> also add a more precise property (first
in order) indicating the board type.</p>
<p>The standard naming is “vendor,name”. For example: <cite>compatible = “goog,rhesus”,”ibm,powernv”;</cite>
would work. Or even better: <cite>compatible = “goog,rhesus-v1”,”goog,rhesus”,”ibm,powernv”;</cite>.</p>
<p>The bare <cite>ibm,powernv</cite> should be reserved for bringup/testing:</p>
<div class="highlight-dts notranslate"><div class="highlight"><pre><span></span><span class="k">/dts-v1/;</span>
<span class="k">/</span> <span class="p">{</span>
<span class="nf">compatible</span> <span class="o">=</span> <span class="s">"ibm,powernv"</span><span class="p">;</span>
<span class="p">};</span>
</pre></div>
</div>
</section>
<section id="example">
<h3>Example<a class="headerlink" href="#example" title="Permalink to this headline">¶</a></h3>
<div class="highlight-dts notranslate"><div class="highlight"><pre><span></span><span class="k">/dts-v1/;</span>
<span class="k">/</span> <span class="p">{</span>
<span class="nf">compatible</span> <span class="o">=</span> <span class="s">"ibm,powernv"</span><span class="p">;</span>
<span class="cm">/* mandatory */</span>
<span class="nf">#address-cells</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x2</span><span class="p">>;</span>
<span class="nf">#size-cells</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x2</span><span class="p">>;</span>
<span class="cm">/* User visible board name (will be shown in /proc/cpuinfo) */</span>
<span class="nf">model</span> <span class="o">=</span> <span class="s">"Machine Name"</span><span class="p">;</span>
<span class="cm">/*</span>
<span class="cm"> * The reserved-names and reserve-names properties work hand in hand. The first one</span>
<span class="cm"> * is a list of strings providing a "name" for each entry in the second one using</span>
<span class="cm"> * the traditional "vendor,name" format.</span>
<span class="cm"> *</span>
<span class="cm"> * The reserved-ranges property contains a list of ranges, each in the form of 2 cells</span>
<span class="cm"> * of address and 2 cells of size (64-bit x2 so each entry is 4 cells) indicating</span>
<span class="cm"> * regions of memory that are reserved and must not be overwritten by skiboot or</span>
<span class="cm"> * subsequently by the Linux Kernel.</span>
<span class="cm"> *</span>
<span class="cm"> * Corresponding entries must also be created in the "reserved map" part of the flat</span>
<span class="cm"> * device-tree (which is a binary list in the header of the fdt).</span>
<span class="cm"> *</span>
<span class="cm"> * Unless a component (skiboot or Linux) specifically knows about a region (usually</span>
<span class="cm"> * based on its name) and decides to change or remove it, all these regions are</span>
<span class="cm"> * passed as-is to Linux and to subsequent kernels across kexec and are kept</span>
<span class="cm"> * preserved.</span>
<span class="cm"> *</span>
<span class="cm"> * NOTE: Do *NOT* copy the entries below, they are just an example and are actually</span>
<span class="cm"> * created by skiboot itself. They represent the SLW image as "detected" by reading</span>
<span class="cm"> * the PBA BARs and skiboot own memory allocations.</span>
<span class="cm"> *</span>
<span class="cm"> * I would recommend that you put in there the SLW and OCC (or HOMER as one block</span>
<span class="cm"> * if that's how you use it) and any additional memory you want to preserve such</span>
<span class="cm"> * as FW log buffers etc...</span>
<span class="cm"> */</span>
<span class="nf">reserved-names</span> <span class="o">=</span> <span class="s">"ibm,slw-image", "ibm,slw-image", "ibm,firmware-stacks", "ibm,firmware-data", "ibm,firmware-heap", "ibm,firmware-code", "memory@400000000"</span><span class="p">;</span>
<span class="nf">reserved-ranges</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x7</span> <span class="mh">0xfe600000</span> <span class="mh">0x0</span> <span class="mh">0x100000</span> <span class="mh">0x7</span> <span class="mh">0xfe200000</span> <span class="mh">0x0</span> <span class="mh">0x100000</span> <span class="mh">0x0</span> <span class="mh">0x31e00000</span> <span class="mh">0x0</span> <span class="mh">0x3e0000</span> <span class="mh">0x0</span> <span class="mh">0x31000000</span> <span class="mh">0x0</span> <span class="mh">0xe00000</span> <span class="mh">0x0</span> <span class="mh">0x30400000</span> <span class="mh">0x0</span> <span class="mh">0xc00000</span> <span class="mh">0x0</span> <span class="mh">0x30000000</span> <span class="mh">0x0</span> <span class="mh">0x400000</span> <span class="mh">0x4</span> <span class="mh">0x0</span> <span class="mh">0x0</span> <span class="mh">0x600450</span><span class="p">>;</span>
<span class="cm">/* Mandatory */</span>
<span class="nc">cpus</span> <span class="p">{</span>
<span class="nf">#address-cells</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x1</span><span class="p">>;</span>
<span class="nf">#size-cells</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span><span class="p">>;</span>
<span class="cm">/*</span>
<span class="cm"> * The following node must exist for each *core* in the system. The unit</span>
<span class="cm"> * address (number after the @) is the hexadecimal HW CPU number (PIR value)</span>
<span class="cm"> * of thread 0 of that core.</span>
<span class="cm"> */</span>
<span class="nc">PowerPC,POWER8</span><span class="nf">@20</span> <span class="p">{</span>
<span class="cm">/* mandatory/standard properties */</span>
<span class="nf">device_type</span> <span class="o">=</span> <span class="s">"cpu"</span><span class="p">;</span>
<span class="nf">64-bit</span><span class="p">;</span>
<span class="nf">32-64-bridge</span><span class="p">;</span>
<span class="nf">graphics</span><span class="p">;</span>
<span class="nf">general-purpose</span><span class="p">;</span>
<span class="cm">/*</span>
<span class="cm"> * The "status" property indicate whether the core is functional. It's</span>
<span class="cm"> * a string containing "okay" for a good core or "bad" for a non-functional</span>
<span class="cm"> * one. You can also just ommit the non-functional ones from the DT</span>
<span class="cm"> */</span>
<span class="nf">status</span> <span class="o">=</span> <span class="s">"okay"</span><span class="p">;</span>
<span class="cm">/*</span>
<span class="cm"> * This is the same value as the PIR of thread 0 of that core</span>
<span class="cm"> * (ie same as the @xx part of the node name)</span>
<span class="cm"> */</span>
<span class="nf">reg</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x20</span><span class="p">>;</span>
<span class="cm">/* same as above */</span>
<span class="nf">ibm,pir</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x20</span><span class="p">>;</span>
<span class="cm">/* chip ID of this core */</span>
<span class="nf">ibm,chip-id</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span><span class="p">>;</span>
<span class="cm">/*</span>
<span class="cm"> * interrupt server numbers (aka HW processor numbers) of all threads</span>
<span class="cm"> * on that core. This should have 8 numbers and the first one should</span>
<span class="cm"> * have the same value as the above ibm,pir and reg properties</span>
<span class="cm"> */</span>
<span class="nf">ibm,ppc-interrupt-server#s</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x20</span> <span class="mh">0x21</span> <span class="mh">0x22</span> <span class="mh">0x23</span> <span class="mh">0x24</span> <span class="mh">0x25</span> <span class="mh">0x26</span> <span class="mh">0x27</span><span class="p">>;</span>
<span class="cm">/*</span>
<span class="cm"> * This is the "architected processor version" as defined in PAPR. Just</span>
<span class="cm"> * stick to 0x0f000004 for P8 and things will be fine</span>
<span class="cm"> */</span>
<span class="nf">cpu-version</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0f000004</span><span class="p">>;</span>
<span class="cm">/*</span>
<span class="cm"> * These are various definitions of the page sizes and segment sizes</span>
<span class="cm"> * supported by the MMU, those values are fine for P8 for now</span>
<span class="cm"> */</span>
<span class="nf">ibm,processor-segment-sizes</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x1c</span> <span class="mh">0x28</span> <span class="mh">0xffffffff</span> <span class="mh">0xffffffff</span><span class="p">>;</span>
<span class="nf">ibm,processor-page-sizes</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0xc</span> <span class="mh">0x10</span> <span class="mh">0x18</span> <span class="mh">0x22</span><span class="p">>;</span>
<span class="nf">ibm,segment-page-sizes</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0xc</span> <span class="mh">0x0</span> <span class="mh">0x3</span> <span class="mh">0xc</span> <span class="mh">0x0</span> <span class="mh">0x10</span> <span class="mh">0x7</span> <span class="mh">0x18</span> <span class="mh">0x38</span> <span class="mh">0x10</span> <span class="mh">0x110</span> <span class="mh">0x2</span> <span class="mh">0x10</span> <span class="mh">0x1</span> <span class="mh">0x18</span> <span class="mh">0x8</span> <span class="mh">0x18</span> <span class="mh">0x100</span> <span class="mh">0x1</span> <span class="mh">0x18</span> <span class="mh">0x0</span> <span class="mh">0x22</span> <span class="mh">0x120</span> <span class="mh">0x1</span> <span class="mh">0x22</span> <span class="mh">0x3</span><span class="p">>;</span>
<span class="cm">/*</span>
<span class="cm"> * Similarly that might need to be reviewed later but will do for now...</span>
<span class="cm"> */</span>
<span class="nf">ibm,pa-features</span> <span class="o">=</span> <span class="p">[</span><span class="mh">0x6</span> <span class="mh">0x0</span> <span class="mh">0xf6</span> <span class="mh">0x3f</span> <span class="mh">0xc7</span> <span class="mh">0x0</span> <span class="mh">0x80</span> <span class="mh">0xc0</span><span class="p">];</span>
<span class="cm">/* SLB size, use as-is */</span>
<span class="nf">ibm,slb-size</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x20</span><span class="p">>;</span>
<span class="cm">/* VSX support, use as-is */</span>
<span class="nf">ibm,vmx</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x2</span><span class="p">>;</span>
<span class="cm">/* DFP support, use as-is */</span>
<span class="nf">ibm,dfp</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x2</span><span class="p">>;</span>
<span class="cm">/* PURR/SPURR support, use as-is */</span>
<span class="nf">ibm,purr</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x1</span><span class="p">>;</span>
<span class="nf">ibm,spurr</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x1</span><span class="p">>;</span>
<span class="cm">/*</span>
<span class="cm"> * Old-style core clock frequency. Only create this property if the frequency fits</span>
<span class="cm"> * in a 32-bit number. Do not create it if it doesn't</span>
<span class="cm"> */</span>
<span class="nf">clock-frequency</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0xf5552d00</span><span class="p">>;</span>
<span class="cm">/*</span>
<span class="cm"> * mandatory: 64-bit version of the core clock frequency, always create this</span>
<span class="cm"> * property.</span>
<span class="cm"> */</span>
<span class="nf">ibm,extended-clock-frequency</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span> <span class="mh">0xf5552d00</span><span class="p">>;</span>
<span class="cm">/* Timebase freq has a fixed value, always use that */</span>
<span class="nf">timebase-frequency</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x1e848000</span><span class="p">>;</span>
<span class="cm">/* Same */</span>
<span class="nf">ibm,extended-timebase-frequency</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span> <span class="mh">0x1e848000</span><span class="p">>;</span>
<span class="cm">/* Use as-is, values might need to be adjusted but that will do for now */</span>
<span class="nf">reservation-granule-size</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x80</span><span class="p">>;</span>
<span class="nf">d-tlb-size</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x800</span><span class="p">>;</span>
<span class="nf">i-tlb-size</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span><span class="p">>;</span>
<span class="nf">tlb-size</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x800</span><span class="p">>;</span>
<span class="nf">d-tlb-sets</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x4</span><span class="p">>;</span>
<span class="nf">i-tlb-sets</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span><span class="p">>;</span>
<span class="nf">tlb-sets</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x4</span><span class="p">>;</span>
<span class="nf">d-cache-block-size</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x80</span><span class="p">>;</span>
<span class="nf">i-cache-block-size</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x80</span><span class="p">>;</span>
<span class="nf">d-cache-size</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x10000</span><span class="p">>;</span>
<span class="nf">i-cache-size</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x8000</span><span class="p">>;</span>
<span class="nf">i-cache-sets</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x4</span><span class="p">>;</span>
<span class="nf">d-cache-sets</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x8</span><span class="p">>;</span>
<span class="nf">performance-monitor</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span> <span class="mh">0x1</span><span class="p">>;</span>
<span class="cm">/*</span>
<span class="cm"> * optional: phandle of the node representing the L2 cache for this core,</span>
<span class="cm"> * note: it can also be named "next-level-cache", Linux will support both</span>
<span class="cm"> * and Sapphire doesn't currently use those properties, just passes them</span>
<span class="cm"> * along to Linux</span>
<span class="cm"> */</span>
<span class="nf">l2-cache</span> <span class="o">=</span> <span class="p"><</span> <span class="mh">0x4</span> <span class="p">>;</span>
<span class="p">};</span>
<span class="cm">/*</span>
<span class="cm"> * Cache nodes. Those are siblings of the processor nodes under /cpus and</span>
<span class="cm"> * represent the various level of caches.</span>
<span class="cm"> *</span>
<span class="cm"> * The unit address (and reg property) is mostly free-for-all as long as</span>
<span class="cm"> * there is no collisions. On HDAT machines we use the following encoding</span>
<span class="cm"> * which I encourage you to also follow to limit surprises:</span>
<span class="cm"> *</span>
<span class="cm"> * L2 : (0x20 << 24) | PIR (PIR is PIR value of thread 0 of core)</span>
<span class="cm"> * L3 : (0x30 << 24) | PIR</span>
<span class="cm"> * L3.5 : (0x35 << 24) | PIR</span>
<span class="cm"> *</span>
<span class="cm"> * In addition, each cache points to the next level cache via its</span>
<span class="cm"> * own "l2-cache" (or "next-level-cache") property, so the core node</span>
<span class="cm"> * points to the L2, the L2 points to the L3 etc...</span>
<span class="cm"> */</span>
<span class="nc">l2-cache</span><span class="nf">@20000020</span> <span class="p">{</span>
<span class="nf">phandle</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x4</span><span class="p">>;</span>
<span class="nf">device_type</span> <span class="o">=</span> <span class="s">"cache"</span><span class="p">;</span>
<span class="nf">reg</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x20000020</span><span class="p">>;</span>
<span class="nf">status</span> <span class="o">=</span> <span class="s">"okay"</span><span class="p">;</span>
<span class="nf">cache-unified</span><span class="p">;</span>
<span class="nf">d-cache-sets</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x8</span><span class="p">>;</span>
<span class="nf">i-cache-sets</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x8</span><span class="p">>;</span>
<span class="nf">d-cache-size</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x80000</span><span class="p">>;</span>
<span class="nf">i-cache-size</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x80000</span><span class="p">>;</span>
<span class="nf">l2-cache</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x5</span><span class="p">>;</span>
<span class="p">};</span>
<span class="nc">l3-cache</span><span class="nf">@30000020</span> <span class="p">{</span>
<span class="nf">phandle</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x5</span><span class="p">>;</span>
<span class="nf">device_type</span> <span class="o">=</span> <span class="s">"cache"</span><span class="p">;</span>
<span class="nf">reg</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x30000020</span><span class="p">>;</span>
<span class="nf">status</span> <span class="o">=</span> <span class="s">"bad"</span><span class="p">;</span>
<span class="nf">cache-unified</span><span class="p">;</span>
<span class="nf">d-cache-sets</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x8</span><span class="p">>;</span>
<span class="nf">i-cache-sets</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x8</span><span class="p">>;</span>
<span class="nf">d-cache-size</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x800000</span><span class="p">>;</span>
<span class="nf">i-cache-size</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x800000</span><span class="p">>;</span>
<span class="p">};</span>
<span class="p">};</span>
<span class="cm">/*</span>
<span class="cm"> * Interrupt presentation controller (ICP) nodes</span>
<span class="cm"> *</span>
<span class="cm"> * There is some flexibility as to how many of these are presents since</span>
<span class="cm"> * a given node can represent multiple ICPs. When generating from HDAT we</span>
<span class="cm"> * chose to create one per core</span>
<span class="cm"> */</span>
<span class="nc">interrupt-controller</span><span class="nf">@3ffff80020000</span> <span class="p">{</span>
<span class="cm">/* Mandatory */</span>
<span class="nf">compatible</span> <span class="o">=</span> <span class="s">"IBM,ppc-xicp", "IBM,power8-icp"</span><span class="p">;</span>
<span class="nf">interrupt-controller</span><span class="p">;</span>
<span class="nf">#address-cells</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span><span class="p">>;</span>
<span class="nf">device_type</span> <span class="o">=</span> <span class="s">"PowerPC-External-Interrupt-Presentation"</span><span class="p">;</span>
<span class="cm">/*</span>
<span class="cm"> * Range of HW CPU IDs represented by that node. In this example</span>
<span class="cm"> * the core starting at PIR 0x20 and 8 threads, which corresponds</span>
<span class="cm"> * to the CPU node of the example above. The property in theory</span>
<span class="cm"> * supports multiple ranges but Linux doesn't.</span>
<span class="cm"> */</span>
<span class="nf">ibm,interrupt-server-ranges</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x20</span> <span class="mh">0x8</span><span class="p">>;</span>
<span class="cm">/*</span>
<span class="cm"> * For each server in the above range, the physical address of the</span>
<span class="cm"> * ICP register block and its size. Since the root node #address-cells</span>
<span class="cm"> * and #size-cells properties are both "2", each entry is thus</span>
<span class="cm"> * 2 cells address and 2 cells size (64-bit each).</span>
<span class="cm"> */</span>
<span class="nf">reg</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x3ffff</span> <span class="mh">0x80020000</span> <span class="mh">0x0</span> <span class="mh">0x1000</span> <span class="mh">0x3ffff</span> <span class="mh">0x80021000</span> <span class="mh">0x0</span> <span class="mh">0x1000</span> <span class="mh">0x3ffff</span> <span class="mh">0x80022000</span> <span class="mh">0x0</span> <span class="mh">0x1000</span> <span class="mh">0x3ffff</span> <span class="mh">0x80023000</span> <span class="mh">0x0</span> <span class="mh">0x1000</span> <span class="mh">0x3ffff</span> <span class="mh">0x80024000</span> <span class="mh">0x0</span> <span class="mh">0x1000</span> <span class="mh">0x3ffff</span> <span class="mh">0x80025000</span> <span class="mh">0x0</span> <span class="mh">0x1000</span> <span class="mh">0x3ffff</span> <span class="mh">0x80026000</span> <span class="mh">0x0</span> <span class="mh">0x1000</span> <span class="mh">0x3ffff</span> <span class="mh">0x80027000</span> <span class="mh">0x0</span> <span class="mh">0x1000</span><span class="p">>;</span>
<span class="p">};</span>
<span class="cm">/*</span>
<span class="cm"> * The "memory" nodes represent physical memory in the system. They</span>
<span class="cm"> * do not represent DIMMs, memory controllers or Centaurs, thus will</span>
<span class="cm"> * be expressed separately.</span>
<span class="cm"> *</span>
<span class="cm"> * In order to be able to handle affinity properly, we require that</span>
<span class="cm"> * a memory node is created for each range of memory that has a different</span>
<span class="cm"> * "affinity", which in practice means for each chip since we don't</span>
<span class="cm"> * support memory interleaved across multiple chips on P8.</span>
<span class="cm"> *</span>
<span class="cm"> * Additionally, it is *not* required that one chip = one memory node,</span>
<span class="cm"> * it is perfectly acceptable to break down the memory of one chip into</span>
<span class="cm"> * multiple memory nodes (typically skiboot does that if the two MCs</span>
<span class="cm"> * are not interlaved).</span>
<span class="cm"> */</span>
<span class="nc">memory</span><span class="nf">@0</span> <span class="p">{</span>
<span class="nf">device_type</span> <span class="o">=</span> <span class="s">"memory"</span><span class="p">;</span>
<span class="cm">/*</span>
<span class="cm"> * We support multiple entries in the ibm,chip-id property for</span>
<span class="cm"> * memory nodes in case the memory is interleaved across multiple</span>
<span class="cm"> * chips but that shouldn't happen on P8</span>
<span class="cm"> */</span>
<span class="nf">ibm,chip-id</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span><span class="p">>;</span>
<span class="cm">/* The "reg" property is 4 cells, as usual for a child of</span>
<span class="cm"> * the root node, 2 cells of address and 2 cells of size</span>
<span class="cm"> */</span>
<span class="nf">reg</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span> <span class="mh">0x0</span> <span class="mh">0x4</span> <span class="mh">0x0</span><span class="p">>;</span>
<span class="p">};</span>
<span class="cm">/*</span>
<span class="cm"> * The XSCOM node. This is the closest thing to a "chip" node we have.</span>
<span class="cm"> * there must be one per chip in the system (thus a DCM has two) and</span>
<span class="cm"> * while it represents the "parent" of various devices on the PIB/PCB</span>
<span class="cm"> * that we want to expose, it is also used to store all sort of</span>
<span class="cm"> * miscellaneous per-chip information on HDAT based systems (such</span>
<span class="cm"> * as VPDs).</span>
<span class="cm"> */</span>
<span class="nc">xscom</span><span class="nf">@3fc0000000000</span> <span class="p">{</span>
<span class="cm">/* standard & mandatory */</span>
<span class="nf">#address-cells</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x1</span><span class="p">>;</span>
<span class="nf">#size-cells</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x1</span><span class="p">>;</span>
<span class="nf">scom-controller</span><span class="p">;</span>
<span class="nf">compatible</span> <span class="o">=</span> <span class="s">"ibm,xscom", "ibm,power8-xscom"</span><span class="p">;</span>
<span class="cm">/* The chip ID as usual ... */</span>
<span class="nf">ibm,chip-id</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span><span class="p">>;</span>
<span class="cm">/* The base address of xscom for that chip */</span>
<span class="nf">reg</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x3fc00</span> <span class="mh">0x0</span> <span class="mh">0x8</span> <span class="mh">0x0</span><span class="p">>;</span>
<span class="cm">/*</span>
<span class="cm"> * This comes from HDAT and I *think* is the raw content of the</span>
<span class="cm"> * module VPD eeprom (and thus doesn't have a standard ASCII keyword</span>
<span class="cm"> * VPD format). We don't currently use it though ...</span>
<span class="cm"> */</span>
<span class="nf">ibm,module-vpd</span> <span class="o">=</span> <span class="p"><</span> <span class="cm">/* ... big pile of binary data ... */</span> <span class="p">>;</span>
<span class="cm">/* PSI host bridge XSCOM register set */</span>
<span class="nc">psihb</span><span class="nf">@2010900</span> <span class="p">{</span>
<span class="nf">reg</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x2010900</span> <span class="mh">0x20</span><span class="p">>;</span>
<span class="nf">compatible</span> <span class="o">=</span> <span class="s">"ibm,power8-psihb-x", "ibm,psihb-x"</span><span class="p">;</span>
<span class="p">};</span>
<span class="cm">/* Chip TOD XSCOM register set */</span>
<span class="nc">chiptod</span><span class="nf">@40000</span> <span class="p">{</span>
<span class="nf">reg</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x40000</span> <span class="mh">0x34</span><span class="p">>;</span>
<span class="nf">compatible</span> <span class="o">=</span> <span class="s">"ibm,power-chiptod", "ibm,power8-chiptod"</span><span class="p">;</span>
<span class="cm">/*</span>
<span class="cm"> * Create that property with no value if this chip has</span>
<span class="cm"> * the Primary TOD in the topology. If it has the secondary</span>
<span class="cm"> * one (backup master ?) use "secondary".</span>
<span class="cm"> */</span>
<span class="nf">primary</span><span class="p">;</span>
<span class="p">};</span>
<span class="cm">/* NX XSCOM register set */</span>
<span class="nc">nx</span><span class="nf">@2010000</span> <span class="p">{</span>
<span class="nf">reg</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x2010000</span> <span class="mh">0x4000</span><span class="p">>;</span>
<span class="nf">compatible</span> <span class="o">=</span> <span class="s">"ibm,power-nx", "ibm,power8-nx"</span><span class="p">;</span>
<span class="p">};</span>
<span class="cm">/*</span>
<span class="cm"> * PCI "PE Master" XSCOM register set for each active PHB</span>
<span class="cm"> *</span>
<span class="cm"> * For now, do *not* create these if the PHB isn't connected,</span>
<span class="cm"> * clocked, or the PHY/HSS not configured.</span>
<span class="cm"> */</span>
<span class="nc">pbcq</span><span class="nf">@2012000</span> <span class="p">{</span>
<span class="nf">reg</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x2012000</span> <span class="mh">0x20</span> <span class="mh">0x9012000</span> <span class="mh">0x5</span> <span class="mh">0x9013c00</span> <span class="mh">0x15</span><span class="p">>;</span>
<span class="nf">compatible</span> <span class="o">=</span> <span class="s">"ibm,power8-pbcq"</span><span class="p">;</span>
<span class="cm">/* Indicate the PHB index on the chip, ie, 0,1 or 2 */</span>
<span class="nf">ibm,phb-index</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span><span class="p">>;</span>
<span class="cm">/* Create that property to use the IBM-style "A/B" dual input</span>
<span class="cm"> * slot presence detect mechanism.</span>
<span class="cm"> */</span>
<span class="nf">ibm,use-ab-detect</span><span class="p">;</span>
<span class="cm">/*</span>
<span class="cm"> * TBD: Lane equalization values. Not currently used by</span>
<span class="cm"> * skiboot but will have to be sorted out</span>
<span class="cm"> */</span>
<span class="nf">ibm,lane_eq</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span><span class="p">>;</span>
<span class="p">};</span>
<span class="nc">pbcq</span><span class="nf">@2012400</span> <span class="p">{</span>
<span class="nf">reg</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x2012400</span> <span class="mh">0x20</span> <span class="mh">0x9012400</span> <span class="mh">0x5</span> <span class="mh">0x9013c40</span> <span class="mh">0x15</span><span class="p">>;</span>
<span class="nf">compatible</span> <span class="o">=</span> <span class="s">"ibm,power8-pbcq"</span><span class="p">;</span>
<span class="nf">ibm,phb-index</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x1</span><span class="p">>;</span>
<span class="nf">ibm,use-ab-detect</span><span class="p">;</span>
<span class="nf">ibm,lane_eq</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span><span class="p">>;</span>
<span class="p">};</span>
<span class="cm">/*</span>
<span class="cm"> * Here's the LPC bus. Ideally each chip has one but in</span>
<span class="cm"> * practice it's ok to only populate the ones actually</span>
<span class="cm"> * used for something. This is not an exact representation</span>
<span class="cm"> * of HW, in that case we would have eccb -> opb -> lpc,</span>
<span class="cm"> * but instead we just have an lpc node and the address is</span>
<span class="cm"> * the base of the ECCB register set for it</span>
<span class="cm"> *</span>
<span class="cm"> * Devices on the LPC are represented as children nodes,</span>
<span class="cm"> * see example below for a standard UART.</span>
<span class="cm"> */</span>
<span class="nc">lpc</span><span class="nf">@b0020</span> <span class="p">{</span>
<span class="cm">/*</span>
<span class="cm"> * Empty property indicating this is the primary</span>
<span class="cm"> * LPC bus. It will be used for the default UART</span>
<span class="cm"> * if any and this is the bus that will be used</span>
<span class="cm"> * by Linux as the virtual 64k of IO ports</span>
<span class="cm"> */</span>
<span class="nf">primary</span><span class="p">;</span>
<span class="cm">/*</span>
<span class="cm"> * 2 cells of address, the first one indicates the</span>
<span class="cm"> * address type, see below</span>
<span class="cm"> */</span>
<span class="nf">#address-cells</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x2</span><span class="p">>;</span>
<span class="nf">#size-cells</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x1</span><span class="p">>;</span>
<span class="nf">reg</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0xb0020</span> <span class="mh">0x4</span><span class="p">>;</span>
<span class="nf">compatible</span> <span class="o">=</span> <span class="s">"ibm,power8-lpc"</span><span class="p">;</span>
<span class="cm">/*</span>
<span class="cm"> * Example device: a UART on IO ports.</span>
<span class="cm"> *</span>
<span class="cm"> * LPC address have 2 cells. The first cell is the</span>
<span class="cm"> * address type as follow:</span>
<span class="cm"> *</span>
<span class="cm"> * 0 : LPC memory space</span>
<span class="cm"> * 1 : LPC IO space</span>
<span class="cm"> * 2: LPC FW space</span>
<span class="cm"> *</span>
<span class="cm"> * (This corresponds to the OPAL_LPC_* arguments</span>
<span class="cm"> * passed to the opal_lpc_read/write functions)</span>
<span class="cm"> *</span>
<span class="cm"> * The unit address follows the old ISA convention</span>
<span class="cm"> * for open firmware which prefixes IO ports with "i".</span>
<span class="cm"> *</span>
<span class="cm"> * (This is not critical and can be 1,3f8 if that's</span>
<span class="cm"> * problematic to generate)</span>
<span class="cm"> */</span>
<span class="nc">serial</span><span class="nf">@i3f8</span> <span class="p">{</span>
<span class="nf">reg</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x1</span> <span class="mh">0x3f8</span> <span class="mi">8</span><span class="p">>;</span>
<span class="nf">compatible</span> <span class="o">=</span> <span class="s">"ns16550", "pnpPNP,501"</span><span class="p">;</span>
<span class="cm">/* Baud rate generator base frequency */</span>
<span class="nf">clock-frequency</span> <span class="o">=</span> <span class="p"><</span> <span class="mi">1843200</span> <span class="p">>;</span>
<span class="cm">/* Default speed to use */</span>
<span class="nf">current-speed</span> <span class="o">=</span> <span class="p"><</span> <span class="mi">115200</span> <span class="p">>;</span>
<span class="cm">/* Historical, helps Linux */</span>
<span class="nf">device_type</span> <span class="o">=</span> <span class="s">"serial"</span><span class="p">;</span>
<span class="cm">/*</span>
<span class="cm"> * Indicate which chip ID the interrupt</span>
<span class="cm"> * is routed to (we assume it will always</span>
<span class="cm"> * be the "host error interrupt" (aka</span>
<span class="cm"> * "TPM interrupt" of that chip).</span>
<span class="cm"> */</span>
<span class="nf">ibm,irq-chip-id</span> <span class="o">=</span> <span class="p"><</span><span class="mh">0x0</span><span class="p">>;</span>
<span class="p">};</span>
<span class="p">};</span>
<span class="p">};</span>
<span class="p">};</span>
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