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<pre class="sourceHeading"> Branch data Line data Source code</pre>
<pre class="source">
<a name="1"><span class="lineNum"> 1 </span> : : // SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later</a>
<a name="2"><span class="lineNum"> 2 </span> : : /* Copyright 2013-2019 IBM Corp. */</a>
<a name="3"><span class="lineNum"> 3 </span> : : </a>
<a name="4"><span class="lineNum"> 4 </span> : : #ifndef __CHIP_H</a>
<a name="5"><span class="lineNum"> 5 </span> : : #define __CHIP_H</a>
<a name="6"><span class="lineNum"> 6 </span> : : </a>
<a name="7"><span class="lineNum"> 7 </span> : : #include <stdint.h></a>
<a name="8"><span class="lineNum"> 8 </span> : : #include <lock.h></a>
<a name="9"><span class="lineNum"> 9 </span> : : </a>
<a name="10"><span class="lineNum"> 10 </span> : : #include <ccan/list/list.h></a>
<a name="11"><span class="lineNum"> 11 </span> : : </a>
<a name="12"><span class="lineNum"> 12 </span> : : /*</a>
<a name="13"><span class="lineNum"> 13 </span> : : * Note on chip IDs:</a>
<a name="14"><span class="lineNum"> 14 </span> : : *</a>
<a name="15"><span class="lineNum"> 15 </span> : : * We carry a "chip_id" around, in the cpu_thread, but also as</a>
<a name="16"><span class="lineNum"> 16 </span> : : * ibm,chip-id properties.</a>
<a name="17"><span class="lineNum"> 17 </span> : : *</a>
<a name="18"><span class="lineNum"> 18 </span> : : * This ID is the HW fabric ID of a chip based on the XSCOM numbering,</a>
<a name="19"><span class="lineNum"> 19 </span> : : * also known as "GCID" (Global Chip ID).</a>
<a name="20"><span class="lineNum"> 20 </span> : : *</a>
<a name="21"><span class="lineNum"> 21 </span> : : * The format of this number is different between chip generations and care must</a>
<a name="22"><span class="lineNum"> 22 </span> : : * be taken when trying to convert between this chip ID and some other</a>
<a name="23"><span class="lineNum"> 23 </span> : : * representation such as PIR values, interrupt-server numbers etc... :</a>
<a name="24"><span class="lineNum"> 24 </span> : : *</a>
<a name="25"><span class="lineNum"> 25 </span> : : */</a>
<a name="26"><span class="lineNum"> 26 </span> : : </a>
<a name="27"><span class="lineNum"> 27 </span> : : /*</a>
<a name="28"><span class="lineNum"> 28 </span> : : * P8 GCID</a>
<a name="29"><span class="lineNum"> 29 </span> : : * -------</a>
<a name="30"><span class="lineNum"> 30 </span> : : *</a>
<a name="31"><span class="lineNum"> 31 </span> : : * Global chip ID is a 6 bit number:</a>
<a name="32"><span class="lineNum"> 32 </span> : : *</a>
<a name="33"><span class="lineNum"> 33 </span> : : * NodeID ChipID</a>
<a name="34"><span class="lineNum"> 34 </span> : : * | | |</a>
<a name="35"><span class="lineNum"> 35 </span> : : * |___|___|___|___|___|___|</a>
<a name="36"><span class="lineNum"> 36 </span> : : *</a>
<a name="37"><span class="lineNum"> 37 </span> : : * The the ChipID is 3 bits long, the GCID is the same as the high bits of PIR</a>
<a name="38"><span class="lineNum"> 38 </span> : : */</a>
<a name="39"><span class="lineNum"> 39 </span> : : #define P8_PIR2GCID(pir) (((pir) >> 7) & 0x3f)</a>
<a name="40"><span class="lineNum"> 40 </span> : : </a>
<a name="41"><span class="lineNum"> 41 </span> : : #define P8_PIR2COREID(pir) (((pir) >> 3) & 0xf)</a>
<a name="42"><span class="lineNum"> 42 </span> : : </a>
<a name="43"><span class="lineNum"> 43 </span> : : #define P8_PIR2THREADID(pir) ((pir) & 0x7)</a>
<a name="44"><span class="lineNum"> 44 </span> : : </a>
<a name="45"><span class="lineNum"> 45 </span> : : /*</a>
<a name="46"><span class="lineNum"> 46 </span> : : * P9 GCID</a>
<a name="47"><span class="lineNum"> 47 </span> : : * -------</a>
<a name="48"><span class="lineNum"> 48 </span> : : *</a>
<a name="49"><span class="lineNum"> 49 </span> : : * Global chip ID is a 7 bit number:</a>
<a name="50"><span class="lineNum"> 50 </span> : : *</a>
<a name="51"><span class="lineNum"> 51 </span> : : * NodeID ChipID</a>
<a name="52"><span class="lineNum"> 52 </span> : : * | | |</a>
<a name="53"><span class="lineNum"> 53 </span> : : * |___|___|___|___|___|___|___|</a>
<a name="54"><span class="lineNum"> 54 </span> : : *</a>
<a name="55"><span class="lineNum"> 55 </span> : : * Bit 56 is unused according to the manual by we add it to the coreid here,</a>
<a name="56"><span class="lineNum"> 56 </span> : : * thus we have a 6-bit core number.</a>
<a name="57"><span class="lineNum"> 57 </span> : : *</a>
<a name="58"><span class="lineNum"> 58 </span> : : * Note: XIVE Only supports 4-bit chip numbers ...</a>
<a name="59"><span class="lineNum"> 59 </span> : : *</a>
<a name="60"><span class="lineNum"> 60 </span> : : * Upper PIR Bits</a>
<a name="61"><span class="lineNum"> 61 </span> : : * --------------</a>
<a name="62"><span class="lineNum"> 62 </span> : : *</a>
<a name="63"><span class="lineNum"> 63 </span> : : * Normal-Core Mode:</a>
<a name="64"><span class="lineNum"> 64 </span> : : * 57:61 CoreID</a>
<a name="65"><span class="lineNum"> 65 </span> : : * 62:63 ThreadID</a>
<a name="66"><span class="lineNum"> 66 </span> : : *</a>
<a name="67"><span class="lineNum"> 67 </span> : : * Fused-Core Mode:</a>
<a name="68"><span class="lineNum"> 68 </span> : : * 57:59 FusedQuadID</a>
<a name="69"><span class="lineNum"> 69 </span> : : * 60 FusedCoreID</a>
<a name="70"><span class="lineNum"> 70 </span> : : * 61:63 FusedThreadID</a>
<a name="71"><span class="lineNum"> 71 </span> : : *</a>
<a name="72"><span class="lineNum"> 72 </span> : : * FusedCoreID 0 contains normal-core chiplet 0 and 1</a>
<a name="73"><span class="lineNum"> 73 </span> : : * FusedCoreID 1 contains normal-core chiplet 2 and 3</a>
<a name="74"><span class="lineNum"> 74 </span> : : *</a>
<a name="75"><span class="lineNum"> 75 </span> : : * Fused cores have interleaved threads:</a>
<a name="76"><span class="lineNum"> 76 </span> : : * core chiplet 0/2 = t0, t2, t4, t6</a>
<a name="77"><span class="lineNum"> 77 </span> : : * core chiplet 1/3 = t1, t3, t5, t7</a>
<a name="78"><span class="lineNum"> 78 </span> : : *</a>
<a name="79"><span class="lineNum"> 79 </span> : : */</a>
<a name="80"><span class="lineNum"> 80 </span> : : #define P9_PIR2GCID(pir) (((pir) >> 8) & 0x7f)</a>
<a name="81"><span class="lineNum"> 81 </span> : : </a>
<a name="82"><span class="lineNum"> 82 </span> : : #define P9_PIR2COREID(pir) (((pir) >> 2) & 0x3f)</a>
<a name="83"><span class="lineNum"> 83 </span> : : </a>
<a name="84"><span class="lineNum"> 84 </span> : : #define P9_PIR2THREADID(pir) ((pir) & 0x3)</a>
<a name="85"><span class="lineNum"> 85 </span> : : </a>
<a name="86"><span class="lineNum"> 86 </span> : : #define P9_GCID2NODEID(gcid) (((gcid) >> 3) & 0xf)</a>
<a name="87"><span class="lineNum"> 87 </span> : : </a>
<a name="88"><span class="lineNum"> 88 </span> : : #define P9_GCID2CHIPID(gcid) ((gcid) & 0x7)</a>
<a name="89"><span class="lineNum"> 89 </span> : : </a>
<a name="90"><span class="lineNum"> 90 </span> : : #define P9_PIR2FUSEDQUADID(pir) (((pir) >> 4) & 0x7)</a>
<a name="91"><span class="lineNum"> 91 </span> : : </a>
<a name="92"><span class="lineNum"> 92 </span> : : #define P9_PIR2FUSEDCOREID(pir) (((pir) >> 3) & 0x1)</a>
<a name="93"><span class="lineNum"> 93 </span> : : </a>
<a name="94"><span class="lineNum"> 94 </span> : : #define P9_PIR2FUSEDTHREADID(pir) ((pir) & 0x7)</a>
<a name="95"><span class="lineNum"> 95 </span> : : </a>
<a name="96"><span class="lineNum"> 96 </span> : : #define P9_PIRFUSED2NORMALCOREID(pir) \</a>
<a name="97"><span class="lineNum"> 97 </span> : : (P9_PIR2FUSEDQUADID(pir) << 2) | \</a>
<a name="98"><span class="lineNum"> 98 </span> : : (P9_PIR2FUSEDCOREID(pir) << 1) | \</a>
<a name="99"><span class="lineNum"> 99 </span> : : (P9_PIR2FUSEDTHREADID(pir) & 1)</a>
<a name="100"><span class="lineNum"> 100 </span> : : </a>
<a name="101"><span class="lineNum"> 101 </span> : : #define P9_PIRFUSED2NORMALTHREADID(pir) (((pir) >> 1) & 0x3)</a>
<a name="102"><span class="lineNum"> 102 </span> : : </a>
<a name="103"><span class="lineNum"> 103 </span> : : #define P10_PIR2FUSEDCOREID(pir) P9_PIR2FUSEDCOREID(pir)</a>
<a name="104"><span class="lineNum"> 104 </span> : : #define P10_PIRFUSED2NORMALCOREID(pir) P9_PIRFUSED2NORMALCOREID(pir)</a>
<a name="105"><span class="lineNum"> 105 </span> : : #define P10_PIRFUSED2NORMALTHREADID(pir) P9_PIRFUSED2NORMALTHREADID(pir)</a>
<a name="106"><span class="lineNum"> 106 </span> : : </a>
<a name="107"><span class="lineNum"> 107 </span> : : /* P9 specific ones mostly used by XIVE */</a>
<a name="108"><span class="lineNum"> 108 </span> : : #define P9_PIR2LOCALCPU(pir) ((pir) & 0xff)</a>
<a name="109"><span class="lineNum"> 109 </span> : : #define P9_PIRFROMLOCALCPU(chip, cpu) (((chip) << 8) | (cpu))</a>
<a name="110"><span class="lineNum"> 110 </span> : : </a>
<a name="111"><span class="lineNum"> 111 </span> : : /*</a>
<a name="112"><span class="lineNum"> 112 </span> : : * P10 PIR</a>
<a name="113"><span class="lineNum"> 113 </span> : : * -------</a>
<a name="114"><span class="lineNum"> 114 </span> : : *</a>
<a name="115"><span class="lineNum"> 115 </span> : : * PIR layout:</a>
<a name="116"><span class="lineNum"> 116 </span> : : *</a>
<a name="117"><span class="lineNum"> 117 </span> : : * | 49| 50| 51| 52| 53| 54| 55| 56| 57| 58| 59| 60| 61| 62| 63|</a>
<a name="118"><span class="lineNum"> 118 </span> : : * |Spare ID |Topology ID |Sp. |Quad ID |Core ID |Thread ID|</a>
<a name="119"><span class="lineNum"> 119 </span> : : *</a>
<a name="120"><span class="lineNum"> 120 </span> : : * Bit 56 is a spare quad ID. In big-core mode, thread ID extends to bit 61.</a>
<a name="121"><span class="lineNum"> 121 </span> : : *</a>
<a name="122"><span class="lineNum"> 122 </span> : : * P10 GCID</a>
<a name="123"><span class="lineNum"> 123 </span> : : * --------</a>
<a name="124"><span class="lineNum"> 124 </span> : : *</a>
<a name="125"><span class="lineNum"> 125 </span> : : * - Global chip ID is also called Topology ID.</a>
<a name="126"><span class="lineNum"> 126 </span> : : * - Node ID is called Group ID (? XXX P10).</a>
<a name="127"><span class="lineNum"> 127 </span> : : *</a>
<a name="128"><span class="lineNum"> 128 </span> : : * Global chip ID is a 4 bit number.</a>
<a name="129"><span class="lineNum"> 129 </span> : : *</a>
<a name="130"><span class="lineNum"> 130 </span> : : * There is a topology mode bit that can be 0 or 1, which changes GCID mapping.</a>
<a name="131"><span class="lineNum"> 131 </span> : : *</a>
<a name="132"><span class="lineNum"> 132 </span> : : * Topology mode 0:</a>
<a name="133"><span class="lineNum"> 133 </span> : : * NodeID ChipID</a>
<a name="134"><span class="lineNum"> 134 </span> : : * | | |</a>
<a name="135"><span class="lineNum"> 135 </span> : : * |____|____|____|____|</a>
<a name="136"><span class="lineNum"> 136 </span> : : *</a>
<a name="137"><span class="lineNum"> 137 </span> : : * Topology mode 1:</a>
<a name="138"><span class="lineNum"> 138 </span> : : * NodeID ChipID</a>
<a name="139"><span class="lineNum"> 139 </span> : : * | | |</a>
<a name="140"><span class="lineNum"> 140 </span> : : * |____|____|____|____|</a>
<a name="141"><span class="lineNum"> 141 </span> : : */</a>
<a name="142"><span class="lineNum"> 142 </span> : : #define P10_PIR2GCID(pir) (((pir) >> 8) & 0xf)</a>
<a name="143"><span class="lineNum"> 143 </span> : : </a>
<a name="144"><span class="lineNum"> 144 </span> : : #define P10_PIR2COREID(pir) (((pir) >> 2) & 0x3f)</a>
<a name="145"><span class="lineNum"> 145 </span> : : </a>
<a name="146"><span class="lineNum"> 146 </span> : : #define P10_PIR2THREADID(pir) ((pir) & 0x3)</a>
<a name="147"><span class="lineNum"> 147 </span> : : </a>
<a name="148"><span class="lineNum"> 148 </span> : : // XXX P10 These depend on the topology mode, how to get that (system type?)</a>
<a name="149"><span class="lineNum"> 149 </span> : : #define P10_GCID2NODEID(gcid, mode) ((mode) == 0 ? ((gcid) >> 1) & 0x7 : ((gcid) >> 2) & 0x3)</a>
<a name="150"><span class="lineNum"> 150 </span> : : #define P10_GCID2CHIPID(gcid, mode) ((mode) == 0 ? (gcid) & 0x1 : (gcid) & 0x3)</a>
<a name="151"><span class="lineNum"> 151 </span> : : </a>
<a name="152"><span class="lineNum"> 152 </span> : : /* P10 specific ones mostly used by XIVE */</a>
<a name="153"><span class="lineNum"> 153 </span> : : #define P10_PIR2LOCALCPU(pir) ((pir) & 0xff)</a>
<a name="154"><span class="lineNum"> 154 </span> : : #define P10_PIRFROMLOCALCPU(chip, cpu) (((chip) << 8) | (cpu))</a>
<a name="155"><span class="lineNum"> 155 </span> : : </a>
<a name="156"><span class="lineNum"> 156 </span> : : struct dt_node;</a>
<a name="157"><span class="lineNum"> 157 </span> : : struct centaur_chip;</a>
<a name="158"><span class="lineNum"> 158 </span> : : struct mfsi;</a>
<a name="159"><span class="lineNum"> 159 </span> : : struct xive;</a>
<a name="160"><span class="lineNum"> 160 </span> : : struct lpcm;</a>
<a name="161"><span class="lineNum"> 161 </span> : : struct vas;</a>
<a name="162"><span class="lineNum"> 162 </span> : : struct p9_sbe;</a>
<a name="163"><span class="lineNum"> 163 </span> : : struct p9_dio;</a>
<a name="164"><span class="lineNum"> 164 </span> : : </a>
<a name="165"><span class="lineNum"> 165 </span> : : /* Chip type */</a>
<a name="166"><span class="lineNum"> 166 </span> : : enum proc_chip_type {</a>
<a name="167"><span class="lineNum"> 167 </span> : : PROC_CHIP_UNKNOWN,</a>
<a name="168"><span class="lineNum"> 168 </span> : : PROC_CHIP_P8_MURANO,</a>
<a name="169"><span class="lineNum"> 169 </span> : : PROC_CHIP_P8_VENICE,</a>
<a name="170"><span class="lineNum"> 170 </span> : : PROC_CHIP_P8_NAPLES,</a>
<a name="171"><span class="lineNum"> 171 </span> : : PROC_CHIP_P9_NIMBUS,</a>
<a name="172"><span class="lineNum"> 172 </span> : : PROC_CHIP_P9_CUMULUS,</a>
<a name="173"><span class="lineNum"> 173 </span> : : PROC_CHIP_P9P,</a>
<a name="174"><span class="lineNum"> 174 </span> : : PROC_CHIP_P10,</a>
<a name="175"><span class="lineNum"> 175 </span> : : };</a>
<a name="176"><span class="lineNum"> 176 </span> : : </a>
<a name="177"><span class="lineNum"> 177 </span> : : /* Simulator quirks */</a>
<a name="178"><span class="lineNum"> 178 </span> : : enum proc_chip_quirks {</a>
<a name="179"><span class="lineNum"> 179 </span> : : QUIRK_NO_CHIPTOD = 0x00000001,</a>
<a name="180"><span class="lineNum"> 180 </span> : : QUIRK_MAMBO_CALLOUTS = 0x00000002,</a>
<a name="181"><span class="lineNum"> 181 </span> : : QUIRK_NO_F000F = 0x00000004,</a>
<a name="182"><span class="lineNum"> 182 </span> : : QUIRK_NO_PBA = 0x00000008,</a>
<a name="183"><span class="lineNum"> 183 </span> : : QUIRK_NO_OCC_IRQ = 0x00000010,</a>
<a name="184"><span class="lineNum"> 184 </span> : : QUIRK_SIMICS = 0x00000020,</a>
<a name="185"><span class="lineNum"> 185 </span> : : QUIRK_SLOW_SIM = 0x00000040,</a>
<a name="186"><span class="lineNum"> 186 </span> : : QUIRK_NO_DIRECT_CTL = 0x00000080,</a>
<a name="187"><span class="lineNum"> 187 </span> : : QUIRK_NO_RNG = 0x00000100,</a>
<a name="188"><span class="lineNum"> 188 </span> : : QUIRK_QEMU = 0x00000200,</a>
<a name="189"><span class="lineNum"> 189 </span> : : QUIRK_AWAN = 0x00000400,</a>
<a name="190"><span class="lineNum"> 190 </span> : : };</a>
<a name="191"><span class="lineNum"> 191 </span> : : </a>
<a name="192"><span class="lineNum"> 192 </span> : : extern enum proc_chip_quirks proc_chip_quirks;</a>
<a name="193"><span class="lineNum"> 193 </span> : : </a>
<a name="194"><span class="lineNum"> 194 </span> :<span class="lineCov"> 38 : static inline bool chip_quirk(unsigned int q)</span></a>
<a name="195"><span class="lineNum"> 195 </span> : : {</a>
<a name="196"><span class="lineNum"> 196 </span> :<span class="lineCov"> 38 : return !!(proc_chip_quirks & q);</span></a>
<a name="197"><span class="lineNum"> 197 </span> : : }</a>
<a name="198"><span class="lineNum"> 198 </span> : : </a>
<a name="199"><span class="lineNum"> 199 </span> : : #define MAX_CHIPS (1 << 6) /* 6-bit chip ID */</a>
<a name="200"><span class="lineNum"> 200 </span> : : </a>
<a name="201"><span class="lineNum"> 201 </span> : : /*</a>
<a name="202"><span class="lineNum"> 202 </span> : : * For each chip in the system, we maintain this structure</a>
<a name="203"><span class="lineNum"> 203 </span> : : *</a>
<a name="204"><span class="lineNum"> 204 </span> : : * This contains fields used by different modules including</a>
<a name="205"><span class="lineNum"> 205 </span> : : * modules in hw/ but is handy to keep per-chip data</a>
<a name="206"><span class="lineNum"> 206 </span> : : */</a>
<a name="207"><span class="lineNum"> 207 </span> : : struct proc_chip {</a>
<a name="208"><span class="lineNum"> 208 </span> : : uint32_t id; /* HW Chip ID (GCID) */</a>
<a name="209"><span class="lineNum"> 209 </span> : : struct dt_node *devnode; /* "xscom" chip node */</a>
<a name="210"><span class="lineNum"> 210 </span> : : </a>
<a name="211"><span class="lineNum"> 211 </span> : : /* These are only initialized after xcom_init */</a>
<a name="212"><span class="lineNum"> 212 </span> : : enum proc_chip_type type;</a>
<a name="213"><span class="lineNum"> 213 </span> : : uint32_t ec_level; /* 0xMm (DD1.0 = 0x10) */</a>
<a name="214"><span class="lineNum"> 214 </span> : : uint8_t ec_rev; /* sub-revision */</a>
<a name="215"><span class="lineNum"> 215 </span> : : </a>
<a name="216"><span class="lineNum"> 216 </span> : : /* Those two values are only populated on machines with an FSP</a>
<a name="217"><span class="lineNum"> 217 </span> : : * dbob_id = Drawer/Block/Octant/Blade (DBOBID)</a>
<a name="218"><span class="lineNum"> 218 </span> : : * pcid = HDAT processor_chip_id</a>
<a name="219"><span class="lineNum"> 219 </span> : : */</a>
<a name="220"><span class="lineNum"> 220 </span> : : uint32_t dbob_id;</a>
<a name="221"><span class="lineNum"> 221 </span> : : uint32_t pcid;</a>
<a name="222"><span class="lineNum"> 222 </span> : : </a>
<a name="223"><span class="lineNum"> 223 </span> : : /* If we expect to have an OCC (i.e. P8) and it is functional,</a>
<a name="224"><span class="lineNum"> 224 </span> : : * set TRUE. If something has told us it is not, set FALSE and</a>
<a name="225"><span class="lineNum"> 225 </span> : : * we can not wait for OCCs to init. This is only going to be</a>
<a name="226"><span class="lineNum"> 226 </span> : : * FALSE in a simulator that doesn't simulate OCCs. */</a>
<a name="227"><span class="lineNum"> 227 </span> : : bool occ_functional;</a>
<a name="228"><span class="lineNum"> 228 </span> : : </a>
<a name="229"><span class="lineNum"> 229 </span> : : /* Used by hw/xscom.c */</a>
<a name="230"><span class="lineNum"> 230 </span> : : uint64_t xscom_base;</a>
<a name="231"><span class="lineNum"> 231 </span> : : </a>
<a name="232"><span class="lineNum"> 232 </span> : : /* Used by hw/lpc.c */</a>
<a name="233"><span class="lineNum"> 233 </span> : : struct lpcm *lpc;</a>
<a name="234"><span class="lineNum"> 234 </span> : : </a>
<a name="235"><span class="lineNum"> 235 </span> : : /* Used by hw/slw.c */</a>
<a name="236"><span class="lineNum"> 236 </span> : : uint64_t slw_base;</a>
<a name="237"><span class="lineNum"> 237 </span> : : uint64_t slw_bar_size;</a>
<a name="238"><span class="lineNum"> 238 </span> : : uint64_t slw_image_size;</a>
<a name="239"><span class="lineNum"> 239 </span> : : </a>
<a name="240"><span class="lineNum"> 240 </span> : : /* Used by hw/homer.c */</a>
<a name="241"><span class="lineNum"> 241 </span> : : uint64_t homer_base;</a>
<a name="242"><span class="lineNum"> 242 </span> : : uint64_t homer_size;</a>
<a name="243"><span class="lineNum"> 243 </span> : : uint64_t occ_common_base;</a>
<a name="244"><span class="lineNum"> 244 </span> : : uint64_t occ_common_size;</a>
<a name="245"><span class="lineNum"> 245 </span> : : uint8_t throttle;</a>
<a name="246"><span class="lineNum"> 246 </span> : : </a>
<a name="247"><span class="lineNum"> 247 </span> : : /* Must hold capi_lock to change */</a>
<a name="248"><span class="lineNum"> 248 </span> : : uint8_t capp_phb3_attached_mask;</a>
<a name="249"><span class="lineNum"> 249 </span> : : uint8_t capp_ucode_loaded;</a>
<a name="250"><span class="lineNum"> 250 </span> : : </a>
<a name="251"><span class="lineNum"> 251 </span> : : /* Used by hw/centaur.c */</a>
<a name="252"><span class="lineNum"> 252 </span> : : struct centaur_chip *centaurs;</a>
<a name="253"><span class="lineNum"> 253 </span> : : </a>
<a name="254"><span class="lineNum"> 254 </span> : : /* Used by hw/p8-i2c.c */</a>
<a name="255"><span class="lineNum"> 255 </span> : : struct list_head i2cms;</a>
<a name="256"><span class="lineNum"> 256 </span> : : </a>
<a name="257"><span class="lineNum"> 257 </span> : : /* Used by hw/psi.c */</a>
<a name="258"><span class="lineNum"> 258 </span> : : struct psi *psi;</a>
<a name="259"><span class="lineNum"> 259 </span> : : </a>
<a name="260"><span class="lineNum"> 260 </span> : : /* Used by hw/fsi-master.c */</a>
<a name="261"><span class="lineNum"> 261 </span> : : struct mfsi *fsi_masters;</a>
<a name="262"><span class="lineNum"> 262 </span> : : </a>
<a name="263"><span class="lineNum"> 263 </span> : : /* Used by hw/xive.c */</a>
<a name="264"><span class="lineNum"> 264 </span> : : struct xive *xive;</a>
<a name="265"><span class="lineNum"> 265 </span> : : </a>
<a name="266"><span class="lineNum"> 266 </span> : : struct vas *vas;</a>
<a name="267"><span class="lineNum"> 267 </span> : : </a>
<a name="268"><span class="lineNum"> 268 </span> : : /* Used by hw/nx-compress.c */</a>
<a name="269"><span class="lineNum"> 269 </span> : : uint64_t nx_base;</a>
<a name="270"><span class="lineNum"> 270 </span> : : /* location code of this chip */</a>
<a name="271"><span class="lineNum"> 271 </span> : : const uint8_t *loc_code;</a>
<a name="272"><span class="lineNum"> 272 </span> : : </a>
<a name="273"><span class="lineNum"> 273 </span> : : /* Used by hw/sbe-p9.c */</a>
<a name="274"><span class="lineNum"> 274 </span> : : struct p9_sbe *sbe;</a>
<a name="275"><span class="lineNum"> 275 </span> : : </a>
<a name="276"><span class="lineNum"> 276 </span> : : /* Used by hw/dio-p9.c */</a>
<a name="277"><span class="lineNum"> 277 </span> : : struct p9_dio *dio;</a>
<a name="278"><span class="lineNum"> 278 </span> : : </a>
<a name="279"><span class="lineNum"> 279 </span> : : /* Used during OCC init */</a>
<a name="280"><span class="lineNum"> 280 </span> : : bool ex_present;</a>
<a name="281"><span class="lineNum"> 281 </span> : : </a>
<a name="282"><span class="lineNum"> 282 </span> : : /* Used by hw/vas.c on p10 */</a>
<a name="283"><span class="lineNum"> 283 </span> : : uint32_t primary_topology;</a>
<a name="284"><span class="lineNum"> 284 </span> : : };</a>
<a name="285"><span class="lineNum"> 285 </span> : : </a>
<a name="286"><span class="lineNum"> 286 </span> : : extern uint32_t pir_to_chip_id(uint32_t pir);</a>
<a name="287"><span class="lineNum"> 287 </span> : : </a>
<a name="288"><span class="lineNum"> 288 </span> : : /*</a>
<a name="289"><span class="lineNum"> 289 </span> : : * Note: In P9 fused-core mode, these will return the "normal"</a>
<a name="290"><span class="lineNum"> 290 </span> : : * core ID and thread ID (ie, thread ID 0..3)</a>
<a name="291"><span class="lineNum"> 291 </span> : : */</a>
<a name="292"><span class="lineNum"> 292 </span> : : extern uint32_t pir_to_core_id(uint32_t pir);</a>
<a name="293"><span class="lineNum"> 293 </span> : : extern uint32_t pir_to_thread_id(uint32_t pir);</a>
<a name="294"><span class="lineNum"> 294 </span> : : </a>
<a name="295"><span class="lineNum"> 295 </span> : : /* In P9 fused core mode, this is the "fused" core ID, in</a>
<a name="296"><span class="lineNum"> 296 </span> : : * normal core mode or P8, this is the same as pir_to_core_id</a>
<a name="297"><span class="lineNum"> 297 </span> : : */</a>
<a name="298"><span class="lineNum"> 298 </span> : : extern uint32_t pir_to_fused_core_id(uint32_t pir);</a>
<a name="299"><span class="lineNum"> 299 </span> : : </a>
<a name="300"><span class="lineNum"> 300 </span> : : extern struct proc_chip *next_chip(struct proc_chip *chip);</a>
<a name="301"><span class="lineNum"> 301 </span> : : </a>
<a name="302"><span class="lineNum"> 302 </span> : : #define for_each_chip(__c) for (__c=next_chip(NULL); __c; __c=next_chip(__c))</a>
<a name="303"><span class="lineNum"> 303 </span> : : </a>
<a name="304"><span class="lineNum"> 304 </span> : : extern struct proc_chip *get_chip(uint32_t chip_id);</a>
<a name="305"><span class="lineNum"> 305 </span> : : </a>
<a name="306"><span class="lineNum"> 306 </span> : : extern void init_chips(void);</a>
<a name="307"><span class="lineNum"> 307 </span> : : </a>
<a name="308"><span class="lineNum"> 308 </span> : : /* helper to get number of chips in the system */</a>
<a name="309"><span class="lineNum"> 309 </span> : : static inline int nr_chips(void)</a>
<a name="310"><span class="lineNum"> 310 </span> : : {</a>
<a name="311"><span class="lineNum"> 311 </span> : : struct proc_chip *chip;</a>
<a name="312"><span class="lineNum"> 312 </span> : : int nr_chips = 0;</a>
<a name="313"><span class="lineNum"> 313 </span> : : </a>
<a name="314"><span class="lineNum"> 314 </span> : : for_each_chip(chip)</a>
<a name="315"><span class="lineNum"> 315 </span> : : nr_chips++;</a>
<a name="316"><span class="lineNum"> 316 </span> : : </a>
<a name="317"><span class="lineNum"> 317 </span> : : return nr_chips;</a>
<a name="318"><span class="lineNum"> 318 </span> : : }</a>
<a name="319"><span class="lineNum"> 319 </span> : : </a>
<a name="320"><span class="lineNum"> 320 </span> : : /* helper to get location code of a chip */</a>
<a name="321"><span class="lineNum"> 321 </span> : : static inline const char *chip_loc_code(uint32_t chip_id)</a>
<a name="322"><span class="lineNum"> 322 </span> : : {</a>
<a name="323"><span class="lineNum"> 323 </span> : : struct proc_chip *chip;</a>
<a name="324"><span class="lineNum"> 324 </span> : : </a>
<a name="325"><span class="lineNum"> 325 </span> : : chip = get_chip(chip_id);</a>
<a name="326"><span class="lineNum"> 326 </span> : : if (!chip)</a>
<a name="327"><span class="lineNum"> 327 </span> : : return NULL;</a>
<a name="328"><span class="lineNum"> 328 </span> : : </a>
<a name="329"><span class="lineNum"> 329 </span> : : return chip->loc_code;</a>
<a name="330"><span class="lineNum"> 330 </span> : : }</a>
<a name="331"><span class="lineNum"> 331 </span> : : </a>
<a name="332"><span class="lineNum"> 332 </span> : : #endif /* __CHIP_H */</a>
<a name="333"><span class="lineNum"> 333 </span> : : </a>
</pre>
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