From 7ddbfb98fdb88b229d829d7c1d5265a722e708af Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Wed, 26 Apr 2017 20:05:47 +1000 Subject: nx: Add POWER9 DARN support This sets up the per chip RNG MMIO BAR and points the per core DARN BAR at it. This is needed on P9 to enabled the DARN instruction (otherwise it'll cause a xstop). This includes a minor rework of some #defines to abstract MMIO definitions. Signed-off-by: Michael Neuling Signed-off-by: Stewart Smith --- include/chip.h | 1 + include/xscom-p9-regs.h | 11 +++++++++++ 2 files changed, 12 insertions(+) (limited to 'include') diff --git a/include/chip.h b/include/chip.h index 588db9f..b957e45 100644 --- a/include/chip.h +++ b/include/chip.h @@ -131,6 +131,7 @@ enum proc_chip_quirks { QUIRK_SIMICS = 0x00000020, QUIRK_SLOW_SIM = 0x00000040, QUIRK_NO_DIRECT_CTL = 0x00000080, + QUIRK_NO_RNG = 0x00000100, }; extern enum proc_chip_quirks proc_chip_quirks; diff --git a/include/xscom-p9-regs.h b/include/xscom-p9-regs.h index 04ec557..2dbad44 100644 --- a/include/xscom-p9-regs.h +++ b/include/xscom-p9-regs.h @@ -7,6 +7,17 @@ #define P9X_EX_NCU_SPEC_BAR_ENABLE PPC_BIT(0) #define P9X_EX_NCU_SPEC_BAR_256K PPC_BIT(1) #define P9X_EX_NCU_SPEC_BAR_ADDRMSK 0x0fffffffffffc000ull /* naturally aligned */ + +#define MMIO_CHIP_STRIDE 0x0000040000000000ull + +#define P9X_NX_MMIO_BAR 0x201108d +#define P9X_NX_MMIO_BAR_EN PPC_BIT(52) +#define P9X_NX_MMIO_OFFSET 0x00060302031d0000ull + +#define P9X_NX_RNG_CFG 0x20110E0 +#define P9X_NX_RNG_CFG_EN PPC_BIT(63) + #define P9X_EX_NCU_DARN_BAR 0x11011 +#define P9X_EX_NCU_DARN_BAR_EN PPC_BIT(0) #endif /* __XSCOM_P9_REGS_H__ */ -- cgit v1.1