From 5d86cebd53683d055f039dbecf3f74fb0084ea83 Mon Sep 17 00:00:00 2001 From: Nicholas Piggin Date: Tue, 8 Jan 2019 00:04:28 +1000 Subject: core/exceptions: implement support for MCE interrupts in powersave The ISA specifies that MCE interrupts in power saving modes will enter at 0x200 with powersave bits in SRR1 set. This is not currently supported properly, the MCE will just happen like a normal interrupt, but GPRs could be lost, which would lead to crashes (e.g., r1, r2, r13 etc). So check the power save bits similarly to the sreset vector, and handle this properly. Signed-off-by: Nicholas Piggin Signed-off-by: Stewart Smith --- include/processor.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/processor.h') diff --git a/include/processor.h b/include/processor.h index 0a93430..edcc210 100644 --- a/include/processor.h +++ b/include/processor.h @@ -92,6 +92,7 @@ #define SPR_SRR1_PM_WAKE_MASK 0x3c0000 /* PM wake reason for P8/9 */ #define SPR_SRR1_PM_WAKE_SRESET 0x100000 +#define SPR_SRR1_PM_WAKE_MCE 0x3c0000 /* Use reserved value for MCE */ /* Bits in LPCR */ -- cgit v1.1