From 7ddbfb98fdb88b229d829d7c1d5265a722e708af Mon Sep 17 00:00:00 2001
From: Michael Neuling <mikey@neuling.org>
Date: Wed, 26 Apr 2017 20:05:47 +1000
Subject: nx: Add POWER9 DARN support

This sets up the per chip RNG MMIO BAR and points the per core DARN
BAR at it.

This is needed on P9 to enabled the DARN instruction (otherwise it'll
cause a xstop).

This includes a minor rework of some #defines to abstract MMIO
definitions.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
---
 hw/nx.c   | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 hw/phb4.c |  2 +-
 2 files changed, 53 insertions(+), 1 deletion(-)

(limited to 'hw')

diff --git a/hw/nx.c b/hw/nx.c
index 83528d1..1391dfb 100644
--- a/hw/nx.c
+++ b/hw/nx.c
@@ -21,11 +21,63 @@
 #include <io.h>
 #include <cpu.h>
 #include <nx.h>
+#include <chip.h>
+#include <xscom-p9-regs.h>
+
+#define MMIO_CALC(__c, __b) \
+	(MMIO_CHIP_STRIDE * (__c) | __b)
+
+extern void nx_p9_rng_init(void);
+
+void nx_p9_rng_init(void)
+{
+	struct proc_chip *chip;
+	struct cpu_thread *c;
+	uint64_t bar, tmp;
+
+	if (proc_gen != proc_gen_p9)
+		return;
+	if (chip_quirk(QUIRK_NO_RNG))
+		return;
+
+	/*
+	 * Two things we need to setup here:
+	 *
+	 * 1) The per chip BAR for the NX RNG region. The location of
+	 *    this is determined by the global MMIO Map.
+
+	 * 2) The per core BAR for the DARN BAR, which points to the
+	 *    per chip RNG region set in 1.
+	 *
+	 */
+	for_each_chip(chip) {
+		/* 1) NX RNG BAR */
+		bar = MMIO_CALC(chip->id, P9X_NX_MMIO_OFFSET);
+		xscom_write(chip->id, P9X_NX_MMIO_BAR,
+			    bar | P9X_NX_MMIO_BAR_EN);
+		/* Read config register for pace info */
+		xscom_read(chip->id, P9X_NX_RNG_CFG, &tmp);
+		prlog(PR_INFO, "%x NX RNG pace:%lli)\n", chip->id,
+		      0xffff & (tmp >> 2));
+
+		/* 2) DARN BAR */
+		for_each_available_core_in_chip(c, chip->id) {
+			uint64_t addr;
+			addr = XSCOM_ADDR_P9_EX(pir_to_core_id(c->pir),
+						P9X_EX_NCU_DARN_BAR);
+			xscom_write(chip->id, addr,
+				    bar | P9X_EX_NCU_DARN_BAR_EN);
+		}
+	}
+}
+
 
 void nx_init(void)
 {
 	struct dt_node *node;
 
+	nx_p9_rng_init();
+
 	dt_for_each_compatible(dt_root, node, "ibm,power-nx") {
 		nx_create_rng_node(node);
 		nx_create_crypto_node(node);
diff --git a/hw/phb4.c b/hw/phb4.c
index e9c59c5..12e17bd 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -53,6 +53,7 @@
 #include <chip.h>
 #include <chiptod.h>
 #include <xive.h>
+#include <xscom-p9-regs.h>
 
 /* Enable this to disable error interrupts for debug purposes */
 #define DISABLE_ERR_INTS
@@ -3408,7 +3409,6 @@ static void phb4_create(struct dt_node *np)
 }
 
 /* Hack for assigning global MMIO space */
-#define MMIO_CHIP_STRIDE 0x0000040000000000ULL
 #define	PHB_BAR_BASE     0x000600c3c0000000ULL
 #define	PHB_BAR_SIZE     0x0000000000100000ULL
 #define	ESB_BAR_BASE     0x000600c300000000ULL
-- 
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