From 51cba86cb6078585ee595be7c82a217ec3f8ef68 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 22 Dec 2016 14:17:04 +1100 Subject: xive: Fix memory barrier in opal_xive_get_xirr() We can do the Ack cycle using a simple load but we need a sync before we look at the EQs, otherwise we might be missing the EQ update corresponding to a priority in the ACK cycle. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Stewart Smith --- hw/xive.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'hw') diff --git a/hw/xive.c b/hw/xive.c index 42655a4..81dc0f5 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -3029,9 +3029,10 @@ static int64_t opal_xive_get_xirr(uint32_t *out_xirr, bool just_poll) /* Perform the HV Ack cycle */ if (just_poll) - ack = in_be64(xs->tm_ring1 + TM_QW3_HV_PHYS) >> 48; + ack = __in_be64(xs->tm_ring1 + TM_QW3_HV_PHYS) >> 48; else - ack = in_be16(xs->tm_ring1 + TM_SPC_ACK_HV_REG); + ack = __in_be16(xs->tm_ring1 + TM_SPC_ACK_HV_REG); + sync(); xive_cpu_vdbg(c, "get_xirr,%s=%04x\n", just_poll ? "POLL" : "ACK", ack); /* Capture the old CPPR which we will return with the interrupt */ -- cgit v1.1