From 1cf5e13ae554cadeb1abedd9c5cafc0d7bd56a16 Mon Sep 17 00:00:00 2001
From: Haren Myneni <haren@linux.ibm.com>
Date: Wed, 4 Aug 2021 12:51:02 +0530
Subject: NX: Set VAS RMA write BAR register on P10

For each NX instance, VAS RMA write BAR register should be set with
the corresponding VAS RMA BAR value.

Refer section: 5.30 VAS RMA write BAR (P10 NX work Book V1.01)

Signed-off-by: Haren Myneni <haren@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
---
 hw/nx-compress.c | 36 ++++++++++++++++++++++++++++++++++++
 hw/vas.c         | 18 ++++++++++++++++++
 2 files changed, 54 insertions(+)

(limited to 'hw')

diff --git a/hw/nx-compress.c b/hw/nx-compress.c
index b230286..9b3c671 100644
--- a/hw/nx-compress.c
+++ b/hw/nx-compress.c
@@ -115,6 +115,30 @@ static int nx_cfg_umac_status_ctrl(u32 gcid, u64 xcfg)
 	return rc;
 }
 
+static int nx_cfg_vas_rma_bar(u32 gcid, u64 xcfg)
+{
+	int rc = 0;
+	u64 cfg;
+
+	cfg = vas_get_rma_bar(gcid);
+	/*
+	 * NOTE: Write the entire bar address to SCOM. VAS/NX will extract
+	 *	 the relevant (NX_P10_VAS_RMA_WRITE_BAR) bits. IOW, _don't_
+	 *	 just write the bit field like:
+	 *	 cfg = SETFIELD(NX_P10_VAS_RMA_WRITE_BAR, 0ULL, cfg);
+	 */
+	rc = xscom_write(gcid, xcfg, cfg);
+
+	if (rc)
+		prerror("NX%d: ERROR: VAS RMA WRITE BAR, %d\n", gcid, rc);
+	else
+		prlog(PR_DEBUG, "NX%d: VAS RMA WRITE BAR, 0x%016lx, "
+				"xcfg 0x%llx\n", gcid, (unsigned long)cfg,
+				xcfg);
+
+	return rc;
+}
+
 int nx_cfg_rx_fifo(struct dt_node *node, const char *compat,
 			const char *priority, u32 gcid, u32 pid, u32 tid,
 			u64 umac_bar, u64 umac_notify)
@@ -272,6 +296,10 @@ void nx_create_compress_node(struct dt_node *node)
 
 	prlog(PR_INFO, "NX%d: 842 at 0x%x\n", gcid, pb_base);
 
+	/*
+	 * ibm,power9-nx is compatible on P10. So using same
+	 * compatible string.
+	 */
 	if (dt_node_is_compatible(node, "ibm,power9-nx")) {
 		u64 cfg_mmio, cfg_txwc, cfg_uctrl, cfg_dma;
 
@@ -297,6 +325,14 @@ void nx_create_compress_node(struct dt_node *node)
 		if (rc)
 			return;
 
+		if (proc_gen > proc_gen_p9) {
+			u64 cfg_rma = pb_base + NX_P10_VAS_RMA_WRITE_BAR;
+
+			rc = nx_cfg_vas_rma_bar(gcid, cfg_rma);
+			if (rc)
+				return;
+		}
+
 		p9_nx_enable_842(node, gcid, pb_base);
 		p9_nx_enable_gzip(node, gcid, pb_base);
 	} else
diff --git a/hw/vas.c b/hw/vas.c
index 2740086..0dbe0bc 100644
--- a/hw/vas.c
+++ b/hw/vas.c
@@ -281,6 +281,24 @@ static void get_rma_bar(struct proc_chip *chip, uint64_t *val)
 	*val = v;
 }
 
+/* Interface for NX - make sure VAS is fully initialized first */
+__attrconst uint64_t vas_get_rma_bar(int chipid)
+{
+	struct proc_chip *chip;
+	uint64_t addr;
+
+	if (!vas_initialized)
+		return 0ULL;
+
+	chip = get_chip(chipid);
+	if (!chip)
+		return 0ULL;
+
+	get_rma_bar(chip, &addr);
+
+	return addr;
+}
+
 /*
  * Initialize RMA BAR on this chip to correspond to its node/chip id.
  * This will cause VAS to accept paste commands to targeted for this chip.
-- 
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