From 2a7e3d203496a016cc90ce91eeb2c4e680ebd1d2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Wed, 4 Aug 2021 12:51:14 +0530 Subject: hw/phb5: Add support for 'Address-Based Interrupt Trigger' mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PHB5 introduces a new Address-Based Interrupt mode which extends the notification offloading to the ESB pages. When ABT is activated, the PHB maps the interrupt source number into the interrupt command address. The PHB triggers the interrupt using directly the IC ESB page of the interrupt number and does not use the notify page of the IC anymore. The PHB interrrupt configuration under ABT is a little different. The 'Interrupt Notify Base Address' register points to the base address of the IC ESB pages and not to the notify page of the IC anymore as on P9. The 'Interrupt Notify Base Index' register is unused. This should improve overall performance. The P10 IC can handle higher interrupt rates compared to P9 and the PHB latency should be improved under ABT. Debug is easier as the interrupt number is now exposed on the PowerBUS. Signed-off-by: Cédric Le Goater [FB: port to phb4.c] Signed-off-by: Frederic Barrat Signed-off-by: Cédric Le Goater Signed-off-by: Vasant Hegde --- hw/xive2.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'hw/xive2.c') diff --git a/hw/xive2.c b/hw/xive2.c index 49c9467..125e3fb 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -2140,12 +2140,6 @@ uint64_t xive2_get_notify_port(uint32_t chip_id, uint32_t ent) * * P10 might now be randomizing the cache line bits in HW to * balance snoop bus usage - * - * TODO (phb5) : implement "address based triggers" (DD2.0?) - * - * The PHBs would no longer target the notify port page but - * the "base ESB MMIO address" of the ESB/EAS range they are - * allocated. Needs a XIVE API change for the PHBs. */ switch(ent) { case XIVE_HW_SRC_PHBn(0): -- cgit v1.1