From 7e017fa42451a23b4c332200da3db1daafe04f1e Mon Sep 17 00:00:00 2001 From: Reza Arbab Date: Mon, 31 Jul 2017 21:37:05 -0500 Subject: npu2: Set the XTS config2 register POWER9 DD2 has added a new bit we'd like to set: "XTS_CONFIG2_NO_FLUSH_ENA: if enabled, allows MMIO ATSDs to suppress the flush" This has passed sanity tests with 4.12 kernels, which are capable of exercising this capability. Signed-off-by: Reza Arbab Cc: Andrew Donnellan Cc: Frederic Barrat Acked-by: Alistair Popple Signed-off-by: Stewart Smith --- hw/npu2.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'hw/npu2.c') diff --git a/hw/npu2.c b/hw/npu2.c index ae6aeba..3faa366 100644 --- a/hw/npu2.c +++ b/hw/npu2.c @@ -784,6 +784,11 @@ static void npu2_hw_init(struct npu2 *p) val = npu2_read(p, NPU2_XTS_CFG); npu2_write(p, NPU2_XTS_CFG, val | NPU2_XTS_CFG_MMIOSD | NPU2_XTS_CFG_TRY_ATR_RO); + if (!is_p9dd1()) { + val = npu2_read(p, NPU2_XTS_CFG2); + npu2_write(p, NPU2_XTS_CFG2, val | NPU2_XTS_CFG2_NO_FLUSH_ENA); + } + /* Init memory cache directory (MCD) registers. */ phys_map_get(p->chip_id, GPU_MEM, NPU2_LINKS_PER_CHIP - 1, &gpu_min_addr, NULL); -- cgit v1.1