From c1cf0bc90c4185db4962a05980a3a0e3d639b58a Mon Sep 17 00:00:00 2001 From: Madhavan Srinivasan Date: Thu, 22 Jun 2017 17:45:15 +0530 Subject: skiboot/doc: Add doc/imc.rst documentation Add imc.rst documentation to detail the In-Memory Collection Counters infrastructure and interface Acked-by: Michael Neuling Signed-off-by: Madhavan Srinivasan Signed-off-by: Stewart Smith --- doc/imc.rst | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ doc/index.rst | 1 + 2 files changed, 55 insertions(+) create mode 100644 doc/imc.rst (limited to 'doc') diff --git a/doc/imc.rst b/doc/imc.rst new file mode 100644 index 0000000..3324aa3 --- /dev/null +++ b/doc/imc.rst @@ -0,0 +1,54 @@ +.. _imc: + +OPAL/Skiboot In-Memory Collection (IMC) interface Documentation +=============================================================== + +Overview: +--------- + +In-Memory-Collection (IMC) is performance monitoring infrastrcuture +for counters that (once started) can be read from memory at any time by +an operating system. Such counters include those for the Nest and Core +units, enabling continuous monitoring of resource utilisation on the chip. + +The API is agnostic as to how these counters are implemented. For the +Nest units, they're implemented by having microcode in an on-chip +microcontroller and for core units, they are implemented as part of core logic +to gather data and periodically write it to the memory locations. + +Nest (On-Chip, Off-Core) unit: +------------------------------ + +Nest units have dedicated hardware counters which can be programmed +to monitor various chip resources such as memory bandwidth, +xlink bandwidth, alink bandwidth, PCI, NVlink and so on. These Nest +unit PMU counters can be programmed in-band via scom. But alternatively, +programming of these counters and periodically moving the counter data +to memory are offloaded to a hardware engine part of OCC (On-Chip Controller). + +Microcode, starts to run at system boot in OCC complex, initialize these +Nest unit PMUs and periodically accumulate the nest pmu counter values +to memory. List of supported events by the microcode is packages as a DTS +and stored in IMA_CATALOG partition. + +Core unit: +---------- + +Core IMC PMU counters are handled in the core-imc unit. Each core has +4 Core Performance Monitoring Counters (CPMCs) which are used by Core-IMC logic. +Two of these are dedicated to count core cycles and instructions. +The 2 remaining CPMCs have to multiplex 128 events each. + +Core IMC hardware does not support interrupts and it peridocially (based on +sampling duration) fetches the counter data and accumulate to main memory. +Memory to accumulate counter data are refered from "PDBAR" (per-core scom) +and "LDBAR" per-thread spr. + +OPAL APIs: +---------- + +The OPAL API is simple: a call to init a counter type, and calls to +start and stop collection. The memory locations are described in the +device tree. + +See :ref:`opal-imc-counters` and :ref:`device-tree/imc` diff --git a/doc/index.rst b/doc/index.rst index 5464ae2..d350acc 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -34,6 +34,7 @@ Developer Guide and Internals pci-slot xscom-node-bindings xive + imc OPAL ABI -- cgit v1.1