From 4c95b5e04e3c4f72e4005574f67cd6e365d3276f Mon Sep 17 00:00:00 2001 From: Frederic Bonnard Date: Mon, 13 Jun 2016 11:37:09 +0200 Subject: Fix for typos While reviewing the Debian packaging, codespell found those. Most proposed fixes are based on codespell's default dictionnary. Signed-off-by: Frederic Bonnard Reviewed-by: Mukesh Ojha Signed-off-by: Stewart Smith --- doc/device-tree.txt | 10 +++++----- doc/device-tree/ibm,opal.txt | 2 +- doc/error-logging.txt | 2 +- doc/nvlink.txt | 2 +- doc/opal-api/opal-pci-phb-mmio-enable-27.txt | 2 +- doc/opal-api/opal-rtc-read-3.txt | 6 +++--- doc/release-notes/skiboot-5.1.0-beta2.txt | 2 +- doc/release-notes/skiboot-5.1.0.txt | 2 +- doc/release-notes/skiboot-5.1.12.txt | 2 +- doc/release-notes/skiboot-5.1.2.txt | 2 +- doc/release-notes/skiboot-5.2.2.txt | 2 +- 11 files changed, 17 insertions(+), 17 deletions(-) (limited to 'doc') diff --git a/doc/device-tree.txt b/doc/device-tree.txt index a0e4457..a231d53 100644 --- a/doc/device-tree.txt +++ b/doc/device-tree.txt @@ -115,7 +115,7 @@ * * Unless a component (skiboot or Linux) specifically knows about a region (usually * based on its name) and decides to change or remove it, all these regions are - * passed as-is to Linux and to subsequent kernels accross kexec and are kept + * passed as-is to Linux and to subsequent kernels across kexec and are kept * preserved. * * NOTE: Do *NOT* copy the entries below, they are just an example and are actually @@ -189,7 +189,7 @@ ibm,segment-page-sizes = <0xc 0x0 0x3 0xc 0x0 0x10 0x7 0x18 0x38 0x10 0x110 0x2 0x10 0x1 0x18 0x8 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; /* - * Similarily that might need to be reviewed later but will do for now... + * Similarly that might need to be reviewed later but will do for now... */ ibm,pa-features = [0x6 0x0 0xf6 0x3f 0xc7 0x0 0x80 0xc0]; @@ -330,10 +330,10 @@ * do not represent DIMMs, memory controllers or Centaurs, thus will * be expressed separately. * - * In order to be able to handle affinity propertly, we require that + * In order to be able to handle affinity properly, we require that * a memory node is created for each range of memory that has a different * "affinity", which in practice means for each chip since we don't - * support memory interleaved accross multiple chips on P8. + * support memory interleaved across multiple chips on P8. * * Additionally, it is *not* required that one chip = one memory node, * it is perfectly acceptable to break down the memory of one chip into @@ -345,7 +345,7 @@ /* * We support multiple entries in the ibm,chip-id property for - * memory nodes in case the memory is interleaved accross multiple + * memory nodes in case the memory is interleaved across multiple * chips but that shouldn't happen on P8 */ ibm,chip-id = <0x0>; diff --git a/doc/device-tree/ibm,opal.txt b/doc/device-tree/ibm,opal.txt index c89c916..d4dcfb8 100644 --- a/doc/device-tree/ibm,opal.txt +++ b/doc/device-tree/ibm,opal.txt @@ -3,7 +3,7 @@ #size-cells = <0x0>; compatible = "ibm,opal-v2", "ibm,opal-v3"; -; v2 is maintained for possible compatibilty with very, very old kernels +; v2 is maintained for possible compatibility with very, very old kernels ; it will go away at some point in the future. Detect and rely on ibm,opal-v3 ibm,associativity-reference-points = <0x4 0x3>; diff --git a/doc/error-logging.txt b/doc/error-logging.txt index 3d6b2a2..ba47785 100644 --- a/doc/error-logging.txt +++ b/doc/error-logging.txt @@ -52,7 +52,7 @@ Step 1: To report an error, invoke opal_elog_create() with required argument. #define OPAL_INPUT_OUTPUT_ERR_EVT 0x02 /* RESOURCE_DEALLOC: Hotplug events and errors */ #define OPAL_RESOURCE_DEALLOC_ERR_EVT 0x03 - /* MISC: Miscellanous error */ + /* MISC: Miscellaneous error */ #define OPAL_MISC_ERR_EVT 0x04 uint16_t component_id: Component ID of Sapphire component as diff --git a/doc/nvlink.txt b/doc/nvlink.txt index d871d20..5aef539 100644 --- a/doc/nvlink.txt +++ b/doc/nvlink.txt @@ -134,7 +134,7 @@ PCI Device Flag Link Number - Physical link number this emulated PCI device is assoicated + Physical link number this emulated PCI device is associated with. One of 0, 1, 4 or 5 (links 2 & 3 do not exist on Naples). Reserved diff --git a/doc/opal-api/opal-pci-phb-mmio-enable-27.txt b/doc/opal-api/opal-pci-phb-mmio-enable-27.txt index c5b08f4..9bff057 100644 --- a/doc/opal-api/opal-pci-phb-mmio-enable-27.txt +++ b/doc/opal-api/opal-pci-phb-mmio-enable-27.txt @@ -13,7 +13,7 @@ used as a starting point for full documentation. The host calls this function to enable or disable PHB decode of the PCI IO and Memory address spaces below that PHB. Window_num selects an mmio window -within that addres space. Enable set to '1' enables the PHB to decode and +within that address space. Enable set to '1' enables the PHB to decode and forward system real addresses to PCI memory, while enable set to '0' disables PHB decode and forwarding for the address range defined in a particular MMIO window. diff --git a/doc/opal-api/opal-rtc-read-3.txt b/doc/opal-api/opal-rtc-read-3.txt index 70f9520..13a0655 100644 --- a/doc/opal-api/opal-rtc-read-3.txt +++ b/doc/opal-api/opal-rtc-read-3.txt @@ -20,10 +20,10 @@ Calling: Since RTC calls can be pretty slow, OPAL_RTC_READ is likely to first return OPAL_BUSY_EVENT, requiring the caller to wait until the OPAL_EVENT_RTC event -has been signaled. Once the event has been signalled, a subsequent -OPAL_RTC_READ call will retreive the time. Since the OPAL_EVENT_RTC event is +has been signaled. Once the event has been signaled, a subsequent +OPAL_RTC_READ call will retrieve the time. Since the OPAL_EVENT_RTC event is used for both reading and writing the RTC, callers must be able to handle -the event being signalled for a concurrent in flight OPAL_RTC_WRITE rather +the event being signaled for a concurrent in flight OPAL_RTC_WRITE rather than this read request. The following code is one way to correctly issue and then wait for a response: diff --git a/doc/release-notes/skiboot-5.1.0-beta2.txt b/doc/release-notes/skiboot-5.1.0-beta2.txt index 3473d89..ebd7fc0 100644 --- a/doc/release-notes/skiboot-5.1.0-beta2.txt +++ b/doc/release-notes/skiboot-5.1.0-beta2.txt @@ -44,7 +44,7 @@ Over skiboot-5.1.0-beta1, the following bugs have been fixed: to have shared mode. So we have to cut off the first M64 segment, which corresponds to reserved PE#0 in kernel. If the first BAR (for example PF's IOV BAR) requires huge alignment in kernel, we - have to waste huge M64 space to accomodate the alignment. If we + have to waste huge M64 space to accommodate the alignment. If we have reserved PE#256, the waste of M64 space will be avoided. Other changes: diff --git a/doc/release-notes/skiboot-5.1.0.txt b/doc/release-notes/skiboot-5.1.0.txt index 127c975..8558378 100644 --- a/doc/release-notes/skiboot-5.1.0.txt +++ b/doc/release-notes/skiboot-5.1.0.txt @@ -104,7 +104,7 @@ The following bugs have been fixed: to have shared mode. So we have to cut off the first M64 segment, which corresponds to reserved PE#0 in kernel. If the first BAR (for example PF's IOV BAR) requires huge alignment in kernel, we - have to waste huge M64 space to accomodate the alignment. If we + have to waste huge M64 space to accommodate the alignment. If we have reserved PE#256, the waste of M64 space will be avoided. FSP-specific bugs fixed: diff --git a/doc/release-notes/skiboot-5.1.12.txt b/doc/release-notes/skiboot-5.1.12.txt index 6368473..49a7e25 100644 --- a/doc/release-notes/skiboot-5.1.12.txt +++ b/doc/release-notes/skiboot-5.1.12.txt @@ -25,7 +25,7 @@ POWER8 PHB (PCIe) specific: - hw/phb3: Flush cache line after updating P/Q bits When doing an MSI EOI, we update the P and Q bits in the IVE. That causes the corresponding cache line to be dirty in the L3 which will cause a - subsequent update by the PHB (upon recieving the next MSI) to get a few + subsequent update by the PHB (upon receiving the next MSI) to get a few retries until it gets flushed. We improve the situation (and thus performance) by doing a dcbf diff --git a/doc/release-notes/skiboot-5.1.2.txt b/doc/release-notes/skiboot-5.1.2.txt index 6e112a5..e64932e 100644 --- a/doc/release-notes/skiboot-5.1.2.txt +++ b/doc/release-notes/skiboot-5.1.2.txt @@ -31,7 +31,7 @@ Over skiboot-5.1.1, we have the following changes: - build improvements - fixes for two compiler warnings were squashed in 5.1.1 commit, re-introduce the fixes. - - misc complier/static analysis warning fixes + - misc compiler/static analysis warning fixes - gard utility: - If gard tool detects the GUARD PNOR partition is corrupted, it will diff --git a/doc/release-notes/skiboot-5.2.2.txt b/doc/release-notes/skiboot-5.2.2.txt index 603270c..3c65e11 100644 --- a/doc/release-notes/skiboot-5.2.2.txt +++ b/doc/release-notes/skiboot-5.2.2.txt @@ -9,7 +9,7 @@ first released August 17th, 2015. Skiboot 5.2.2 replaces skiboot-5.2.1 as the current stable version, which was released on April 27th, 2016. Over skiboot-5.2.1, skiboot 5.2.2 contains -one bug fix targetted at P8NVL systems, notably the Garrison platform. +one bug fix targeted at P8NVL systems, notably the Garrison platform. skiboot-5.2.2 contains all bug fixes as of skiboot-5.1.16. -- cgit v1.1