From 60ce59ccd0e978b0a2bc05e9048d03378c79a85c Mon Sep 17 00:00:00 2001 From: Gavin Shan Date: Thu, 11 Aug 2016 14:55:16 +1000 Subject: hw/phb3: Disable ECRC on Broadcom adapter behind PMC switch The ECRC generation and check can't be enabled on Broadcom's NIC (14e4:168a) when it seats behind PMC PCIe switch downstream port (11f8:8546). Otherwise, the NIC's config space can not be accessed and returns 0xFF's on read because of EEH error even after the error is cleared. The issue is reported from Firestone. This disables ECRC generation and check on Broadcom's NIC when it seats behind PMC PCIe switch downstream port. With this applied, the NIC can be detected successfully. Reported-by: Li Meng Signed-off-by: Gavin Shan [stewart@linux.vnet.ibm.com: add description of device workaround is for] Signed-off-by: Stewart Smith --- hw/phb3.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/hw/phb3.c b/hw/phb3.c index d0b5010..1796a8f 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -405,6 +405,24 @@ static void phb3_switch_port_init(struct phb *phb, pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, val32); } +static inline bool phb3_endpoint_report_ecrc(struct pci_device *pd) +{ + if (!pd || !pd->parent) + return true; + + /* No ECRC generation and check on Broadcom ethernet adapter + * when it seats behind a PMC's PCIe switch downstream port. + * Otherwise, the Broadcom ethernet adapter's config space + * can't be accessed because of frozen PE error even after + * the frozen PE error is cleared. + */ + if (pd->vdid == 0x168a14e4 || // Broadcom bnx2x CHIP_NUM_57800 + pd->parent->vdid == 0x854611f8) + return false; + + return true; +} + static void phb3_endpoint_init(struct phb *phb, struct pci_device *dev, int ecap, int aercap) @@ -442,8 +460,12 @@ static void phb3_endpoint_init(struct phb *phb, /* Enable ECRC generation and check */ pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, &val32); - val32 |= (PCIECAP_AER_CAPCTL_ECRCG_EN | - PCIECAP_AER_CAPCTL_ECRCC_EN); + if (phb3_endpoint_report_ecrc(dev)) + val32 |= (PCIECAP_AER_CAPCTL_ECRCG_EN | + PCIECAP_AER_CAPCTL_ECRCC_EN); + else + val32 &= ~(PCIECAP_AER_CAPCTL_ECRCG_EN | + PCIECAP_AER_CAPCTL_ECRCC_EN); pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, val32); } -- cgit v1.1