From 5a76659c0c2322f7c70d634cc51779582d25174d Mon Sep 17 00:00:00 2001 From: Alistair Popple Date: Fri, 16 Oct 2015 16:08:20 +1100 Subject: Garrison: Add Nvlink device tree bindings Garrison is the first system to support Nvlink. Eventually Hostboot should provide these device tree bindings. In the meantime this patch will add the required fixups to enable the Nvlinks on Garrison. Signed-off-by: Alistair Popple Signed-off-by: Stewart Smith --- platforms/astbmc/garrison.c | 61 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/platforms/astbmc/garrison.c b/platforms/astbmc/garrison.c index edc3522..57e41d7 100644 --- a/platforms/astbmc/garrison.c +++ b/platforms/astbmc/garrison.c @@ -21,9 +21,67 @@ #include #include #include +#include #include "astbmc.h" +#define NPU_BASE 0x8013c00 +#define NPU_SIZE 0x2c +#define NPU_INDIRECT0 0x8000000008010c3f +#define NPU_INDIRECT1 0x8000000008010c7f + +static void create_link(struct dt_node *npu, struct dt_node *pbcq, int index) +{ + struct dt_node *link; + uint32_t lane_mask; + uint64_t phy; + char namebuf[32]; + + snprintf(namebuf, sizeof(namebuf), "link@%x", index); + link = dt_new(npu, namebuf); + + dt_add_property_string(link, "compatible", "ibm,npu-link"); + dt_add_property_cells(link, "ibm,npu-link-index", index); + + if (index < 4) { + phy = NPU_INDIRECT0; + lane_mask = 0xff << (index * 8); + } else { + phy = NPU_INDIRECT1; + lane_mask = 0xff0000 >> (index - 3) * 8; + } + dt_add_property_u64s(link, "ibm,npu-phy", phy); + dt_add_property_cells(link, "ibm,npu-lane-mask", lane_mask); + dt_add_property_cells(link, "ibm,npu-pbcq", pbcq->phandle); +} + +static void dt_create_npu(void) +{ + struct dt_node *xscom, *npu, *pbcq; + char namebuf[32]; + + dt_for_each_compatible(dt_root, xscom, "ibm,xscom") { + snprintf(namebuf, sizeof(namebuf), "npu@%x", NPU_BASE); + npu = dt_new(xscom, namebuf); + dt_add_property_cells(npu, "reg", NPU_BASE, NPU_SIZE); + dt_add_property_strings(npu, "compatible", "ibm,power8-npu"); + dt_add_property_cells(npu, "ibm,npu-index", 0); + dt_add_property_cells(npu, "ibm,npu-links", 4); + + /* On Garrison we have 2 links per GPU device. The + * first 2 links go to the GPU connected via + * pbcq@2012c00 the second two via pbcq@2012800. */ + pbcq = dt_find_by_name(xscom, "pbcq@2012c00"); + assert(pbcq); + create_link(npu, pbcq, 0); + create_link(npu, pbcq, 1); + pbcq = dt_find_by_name(xscom, "pbcq@2012800"); + assert(pbcq); + create_link(npu, pbcq, 4); + create_link(npu, pbcq, 5); + } +} + static bool garrison_probe(void) { if (!dt_node_is_compatible(dt_root, "ibm,garrison")) @@ -43,6 +101,9 @@ static bool garrison_probe(void) */ psi_set_external_irq_policy(EXTERNAL_IRQ_POLICY_LINUX); + /* Fixups until HB get the NPU bindings */ + dt_create_npu(); + return true; } -- cgit v1.1