From 2c309d71e0b762b19163bb022ec1faba2ea122aa Mon Sep 17 00:00:00 2001 From: Oliver O'Halloran Date: Thu, 27 Aug 2020 13:54:17 +1000 Subject: hw/phb4: Verify AER support before initialising AER regs [ Upstream commit 0a5f2812a7e9007f2a89502a3f07bac34bfacbdb ] Check the AER capability offset pointer is non-zero before enabling the AER messages. If the device doesn't support AER we end up writing garbage to config offset 0x0 + PCIECAP_AER_CAPCTL, or 0x18. For a normal device this is one of the BARs so this doesn't do much, but for a bridge this results in overriding: 0x18 - The primary bus number 0x19 - The secondary bus number 0x1A - The subordinate bus number 0x1B - The latency timer 0x1B is hardwired to zero for PCIe devices, but overwriting the bus number register can cause issues with routing of config space accesses. It's worth pointing out that we write actual values for the secondary and subordinate bus numbers before scanning the secondary bus, but the primary bus number is never restored. Cc: skiboot-stable@lists.ozlabs.org Signed-off-by: Oliver O'Halloran Signed-off-by: Vasant Hegde --- hw/phb4.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/phb4.c b/hw/phb4.c index 567cecf..1be786e 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -788,6 +788,9 @@ static void phb4_endpoint_init(struct phb *phb, pci_cfg_write16(phb, bdfn, ecap + PCICAP_EXP_DEVCTL, val16); /* Enable ECRC generation and check */ + if (!aercap) + return; + pci_cfg_read32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, &val32); val32 |= (PCIECAP_AER_CAPCTL_ECRCG_EN | PCIECAP_AER_CAPCTL_ECRCC_EN); -- cgit v1.1