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Update the platform_ocapi structure to store Rainier platform-specific
values for detecting and resetting OpenCAPI devices via the module
I2C (PCA9553)
The unique number I2C bus ID associated to each OpenCapi device
is get from the I2C port and engine.
(De)Assert a reset and detect an OpenCapi device is available through
the I2C bus id and address.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Skiboot is using r16 as a fixed register containing this CPU pointer,
but we can be called back into from hostboot via the host services
interface, where r16 may have been set by hostboot. Switch this back to
skiboot's CPU pointer before running host services handlers, and then
restore it to the hostboot value before returning.
Fixes: 11ce9612b3aa ("move the __this_cpu register to r16, reserve r13-r15")
Reported-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Tested-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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npu3 was only used on the Swift platform to add support for
GPUs (nvlink). The Swift platform has never left the lab and support
for GPUs on it is pretty much dead. So let's remove it.
The patch removes all related code. Device tree entries are no
longer created and in the very unlikely case that someone is still
trying to boot it, the linux nvlink discovery code should be quiet.
Tested by booting on Swift with no GPU.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Reza Arbab <arbab@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Denali is P10 system. But FSP interaction (MBOX protocol) is same as ZZ.
Hence add denali platform detection code inside zz.c for now. We can think
of adding separate platform later.
Also enable :
- P10 TCE mapping support
- Detect PHBs
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Rainier comes in two variants; 4U and 2U.
PCIe slot power on from oohall with multi-socket support from fbarrat:
On Rainier the PCIe slots have individual slot power controllers. These
need to be enabled at boot so that we can scan the devices in the PHB
root ports.
This should really be integrated into the OPAL slot power control
framework that was used for PCIe Hotplug support on Frienze (P8 FSP
systems). Unfortunately, the way that is implemented is difficult to
extend at best and needs to be refactored before we can add support
for runtime power control on rainier.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
[arbab@linux.ibm.com: Use bmc_plat_ast2600_openbmc]
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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platforms/ibm-fsp/common.c:252:17: error: symbol 'fsp_heartbeat_time' redeclared with different type (different modifiers):
platforms/ibm-fsp/common.c:252:17: int extern [addressable] [pure] [signed] [toplevel] fsp_heartbeat_time( ... )
platforms/ibm-fsp/common.c: note: in included file:
platforms/ibm-fsp/ibm-fsp.h:40:5: note: previously declared as:
platforms/ibm-fsp/ibm-fsp.h:40:5: int extern [addressable] [signed] [toplevel] fsp_heartbeat_time( ... )
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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This just keeps the requested delta and uses it to adjust subsequent
rtc_read calls.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Use the method provided by Frederic:
Add the "ibm, maximum link speed" attribute to the PHB device tree at index 0.
The phb4.c code will looks for it and set up the link correctly.
Signed-off-by: LuluTHSu <Lulu_Su@wistron.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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This reverts commit 5262cdd1b99f77bca5951fc8132f9795ef0c2b87.
When link reset/retrain, this method cannot maintain the max-link-speed limit, so remove it.
Signed-off-by: LuluTHSu <Lulu_Su@wistron.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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platforms/astbmc/witherspoon.c:557:28: warning: Using plain integer as NULL pointer
Signed-off-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Since Mowgli has only one slot, modify the names of other slots to avoid confusion.
Cc: skiboot-stable@lists.ozlabs.org
Signed-off-by: LuluTHSu <Lulu_Su@wistron.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Refer to the spec. of mowgli, limit the slot to Gen3 speed.
For mowgli platform spec.
Cc: skiboot-stable@lists.ozlabs.org
Signed-off-by: LuluTHSu <Lulu_Su@wistron.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Hostboot doesn't export the correct data for the system VPD EEPROM for this system.
So add vpd_dt_fixup().
Cc: skiboot-stable@lists.ozlabs.org
Signed-off-by: LuluTHSu <Lulu_Su@wistron.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Secure variable support is needed for Host OS Secure Boot key management.
This needs to be enabled for each platform, as each platform needs to
select the storage and backend drivers to use. This patch adds secure
variable support to the mowgli platform.
Test Results:
After applying the patch, sysfs and device-tree shows secvar entries correctly.
# cd /sys/firmware/secvar/
# ls
format vars
# cat format
ibm,edk2-compat-v1
# cd vars
# ls
KEK PK TS db dbx
# cat PK/size
0
# cat KEK/size
0
# cat TS/size
64
# cat db/size
0
# cat dbx/size
0
# ls /proc/device-tree/ibm,secureboot/
compatible hw-key-hash-size name secure-enabled
hw-key-hash ibm,cvc phandle trusted-enabled
# ls /proc/device-tree/ibm,opal/secvar/status
/proc/device-tree/ibm,opal/secvar/status
# ls /proc/device-tree/ibm,opal/secvar/
compatible max-var-key-len name status
format max-var-size phandle update-status
# cat /proc/device-tree/ibm,opal/secvar/status
okay#
# cat /proc/device-tree/ibm,opal/secvar/format
ibm,edk2-compat-v1#
Signed-off-by: Nayna Jain <nayna@linux.ibm.com>
Signed-off-by: Klaus Heinrich Kiwi <klaus@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Secure variable support needs to be enabled for each platform, and each
platform needs to select which storage and backend drivers to use (or
alternatively implement their own). This patch adds secure variable
support to the witherspoon platform.
Signed-off-by: Eric Richter <erichte@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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This is the initial version.
Cc: skiboot-stable@lists.ozlabs.org
Cc: skiboot-stable@lists.ozlabs.org # skiboot-op940.x
Signed-off-by: LuluTHSu <Lulu_Su@wistron.com>
Reviewed-by: Dan Horák <dan@danny.cz>
[oliver: fixed up whitepace errors]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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The system is larger than ZZ and uses P9 Cumulus chip.
However the interactions with host is via FSP and
FSP mailbox which are identical to a ZZ platform.
Add the DT string and detect as ZZ to avoid creating
a nearly identical FSP based platform.
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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The commit 6826095 ("platform/mihawk: support dynamic PCIe slot table")
added the IPMI OEM command to communicate with BMC. We do the
ipmi_free_msg(msg) twice that caused the Fast-reboot fail.
This patch fixes it by removing the IPMI double-free bug to restore
Fast-reboot.
Signed-off-by: Nichole Wang <Nichole_Wang@wistron.com>
Cc: skiboot-stable@lists.ozlabs.org # skiboot-6.6.x
Cc: skiboot-stable@lists.ozlabs.org # skiboot-op940.x
Fixes: commit 6826095 ("platform/mihawk: support dynamic PCIe slot table")
Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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The Bittware 250SOC adapter on Mihawk was showing a high count of CRC
errors on one of the opencapi slots. The PHY team suggested new
equalization settings to correct the errors.
All existing adapters have been tested on mihawk to make sure the
settings are compatible. However, the new settings should not be used
on platforms other than mihawk.
The changes specific to mihawk are:
- Update the tx_ffe_pre_coeff and tx_ffe_post_coeff input parameters
used during zcal
- turn off the tx_ffe_boost parameter through scom
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Cc: skiboot-stable@lists.ozlabs.org # skiboot-op940.x
Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Based off the Raptor patch:
https://git.raptorcs.com/git/blackbird-skiboot/commit/?id=c81f9d66592dc2a7cf7f6c59c3def5cee0638c1f
Notable changes:
- slot names matching what's silkscreened on the board
- Expose IPL Observer over op-panel OPAL calls
This means you can "printf '\xfe\xfe\xfe' > /dev/op_panel" to
make the IPL Observer on the Raptor BMC builds to realise it
can turn on fan control.
Signed-off-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Slot table auto-detection for different riser cards by using IPMI OEM command to communicate with BMC.
Signed-off-by: Joy Chu <joy_chu@wistron.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Good GPU direct performance on witherspoon, with a Mellanox adapter
on the shared slot, requires to reallocate some dma engines within
PEC2, "stealing" some from PHB4&5 and giving extras to PHB3. It's
currently done when using CAPI mode. But the same is true if the
adapter stays in PCI mode.
In preparation for upcoming versions of MOFED, which may not use CAPI
mode, this patch reallocates dma engines even in PCI mode for a series
of Mellanox adapters that can be used with GPU direct, on witherspoon
and on the shared slot only.
The loss of dma engines for PHB4&5 on witherspoon has not shown
problems in testing, as well as in current deployments where CAPI mode
is used.
Here is a comparison of the bandwidth numbers seen with the PHB in PCI
mode (no CAPI) with and without this patch. Variations on smaller
packet sizes can be attributed to jitter and are not that meaningful.
# OSU MPI-CUDA Bi-Directional Bandwidth Test v5.6.1
# Send Buffer on DEVICE (D) and Receive Buffer on DEVICE (D)
# Size Bandwidth (MB/s) Bandwidth (MB/s)
# with patch without patch
1 1.29 1.48
2 2.66 3.04
4 5.34 5.93
8 10.68 11.86
16 21.39 23.71
32 42.78 49.15
64 85.43 97.67
128 170.82 196.64
256 385.47 383.02
512 774.68 755.54
1024 1535.14 1495.30
2048 2599.31 2561.60
4096 5192.31 5092.47
8192 9930.30 9566.90
16384 18189.81 16803.42
32768 24671.48 21383.57
65536 28977.71 24104.50
131072 31110.55 25858.95
262144 32180.64 26470.61
524288 32842.23 26961.93
1048576 33184.87 27217.38
2097152 33342.67 27338.08
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Cc: skiboot-stable@lists.ozlabs.org # skiboot-op940.x
Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Cc: Ilya Kuznetsov <ilya@yadro.com>
Cc: Artem Senichev <artemsen@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Cc: Dan Horák <dan@danny.cz>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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The following files contain contributions from Timothy Pearson at Raptor
Computer Systems. He has agreed to re-license these contributions as
Dual Apache 2.0 / GPLv2+, so amend the SPDX tag to reflect that.
hw/phb4.c
include/phb4.h
include/platform.h
platforms/astbmc/talos.c
platforms/astbmc/romulus.c
Cc: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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SPDX makes it a simpler diff.
I have audited the commit history of each file to ensure that they are
exclusively authored by IBM and thus we have the right to relicense.
The motivation behind this is twofold:
1) We want to enable experiments with coreboot, which is GPLv2 licensed
2) An upcoming firmware component wants to incorporate code from skiboot
and code from the Linux kernel, which is GPLv2 licensed.
I have gone through the IBM internal way of gaining approval for this.
The following files are not exclusively authored by IBM, so are *not*
included in this update (I will be seeking approval from contributors):
core/direct-controls.c
core/flash.c
core/pcie-slot.c
external/common/arch_flash_unknown.c
external/common/rules.mk
external/gard/Makefile
external/gard/rules.mk
external/opal-prd/Makefile
external/pflash/Makefile
external/xscom-utils/Makefile
hdata/vpd.c
hw/dts.c
hw/ipmi/ipmi-watchdog.c
hw/phb4.c
include/cpu.h
include/phb4.h
include/platform.h
libflash/libffs.c
libstb/mbedtls/sha512.c
libstb/mbedtls/sha512.h
platforms/astbmc/barreleye.c
platforms/astbmc/garrison.c
platforms/astbmc/mihawk.c
platforms/astbmc/nicole.c
platforms/astbmc/p8dnu.c
platforms/astbmc/p8dtu.c
platforms/astbmc/p9dsu.c
platforms/astbmc/vesnin.c
platforms/rhesus/ec/config.h
platforms/rhesus/ec/gpio.h
platforms/rhesus/gpio.c
platforms/rhesus/rhesus.c
platforms/astbmc/talos.c
platforms/astbmc/romulus.c
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
[oliver: fixed up the drift]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Add nvme slot table for broadcom gen4 nvme hba card support.
Signed-off-by: Joy Chu <joy_chu@wistron.com>
[oliver: fixed statment with no effect warning]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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The 0xEF return code is used to tell the hypervisor that the FSP was not
able to replicate an NVRAM write to the secondary FSP. The GENERIC_FAILURE
is using this code instead of the correct 0xFE code which indicates a
generic error condition.
We already have a FSP_STATUS_GENERIC_ERROR for 0xFE so convert the
existing users of FSP_STATUS_GENERIC_FAILURE to use GENERIC_ERROR
and remove the duplicate.
Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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If ibm,slot-location-code isn't in a PCI device's parent node the loop
to search for it will never terminate since p = np->parent is always
going to return the same result.
Fixes: ab1b05d29f5e ("PCI: create optional loc-code platform callback")
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Some platforms (mostly OpenPower-based) will favor a short,
slot-label-based string for the "ibm,loc-code" DT property. Other
platforms such as ZZ/FSP-based platforms will prefer the fully-qualified
slot-location-code for it.
This patches creates a new operation on the platform struct, allowing
for an optional callback to create the "ibm,loc-code" property in a
platform-specific way. If the callback is not defined, use the
cleaned-up default that was in use so far.
Signed-off-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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This patch lets each platform define the name of the opencapi
slots. It makes it easier to identify which physical card is
generating errors or messages in the linux or skiboot log files.
The patch provides slot names for mihawk and witherspoon. If the
platform doesn't define any, then we default to 'OPENCAPI-xxxx'
There are various ways to find out about the slot names:
skiboot log
lspci command (if the PCI hotplug driver pnv-php is loaded)
lshw
checking the device tree
and probably others....
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Certain FSP configurations include PCIe switches that can have LXVPD
slot map entries using the same switch-id and dev-id, even if they are
referring to different upstream and downstream ports of the same link.
The slot matching function (lxvpd_get_slot()) will match the first
occurence, that can be the upstream port with, and ignore the downstream
port.
The main symptom for the above is an incorrect label for those slots,
but I believe other slot attributes could be incorrect as well (as we
are associating a slot with an upstream port).
This patch picks-up an existing "upstream port" attribute from the 1005
version of the LXVPD slot map to prevent matching upstream ports on
the slot matching function.
Signed-off-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com>
[oliver: 80cols compliance]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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In some corner cases, FSP may not respond to Deep IPL request after
code update -OR- it may delay processing MBOX command. In such cases
we may enter code update path again.. which is not required.
Hence clear flash hook after completing code update.
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Hostboot doesn't export the correct description for EEPROMs,
as a result, all EEPROMs in the system work in "atmel,24c128"
compatibility mode (16KiB).
Nicole platform has 32KiB EEPROM for the system VPD.
Signed-off-by: Artem Senichev <a.senichev@yadro.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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The 'ibm,phb-index' property of the NPU node is now useless, as we can
have multiple PHBs associated to the same NPU on P9. Let's remove it
to avoid confusion.
Reviewed-by: Reza Arbab <arbab@linux.ibm.com>
Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Should be no real code change, these mostly update type declarations
that sparse complains about.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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This fixes quite a few sparse endian annotations across the tree.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Convert memconsole dt construction and in-memory tables to use
explicit endian conversions.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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This adds missing endian conversions to most calls, sufficient at least
to handle calls from a kernel booting on mambo.
Subsystems requiring more extensive changes (e.g., xive) will be done
with individual changes.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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On witherspoon there's an I2C bus connecting the each chip to the GPUs
connected to that chip via NVLink. That bus has a 750kOhm pullup on the
system planar with prevents the bus from operating correctly.
Each GPU has a smaller pullup which makes the bus usable when a GPU is
plugged in, but on systems without GPUs we get a lot of spurious I2C
master errors. Specificly, because of the oversized pullup the SDA and
SCL for that bus cannot return to '1' fast enough, so the master assumes
that another master is driving the bus and that it should stop.
Work around this by disabling the affected port when there's no GPUs
detected in the system.
Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Add VPD EEPROM type fix for planar VPD update.
Signed-off-by: Joy Chu <joy_chu@wistron.com>
[oliver: commit subject]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Newer firmware declares the system as "ibm,mihawk", but the labs are
full of older installs, which were using "wistron,mihawk". Let's keep
detecting the older string since it allows to run recent skiboot on
older fw stack and make people's lives a little tiny bit easier.
Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
Reviewed-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Prepare ground for the QEMU simulator which will export "qemu,powernv10"
machines when available. BMC is still defined as ast2500 but it should
change to ast2600 in the future.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Add a more complex slot table example to the Qemu platform. A more complex
PCIe topology in qemu is useful for testing and it's simple enough to
serve as an good example of how to use the slot table construction macros.
Test in Qemu with:
./qemu-system-ppc64 -machine powernv -nographic -m 2G \
-bios ./skiboot.lid -kernel ./vmlinux -initrd ./petitfs \
-device x3130-upstream,id=sw0_up,bus=pcie.2 \
-device xio3130-downstream,id=sw0_down0,chassis=1,slot=0,bus=sw0_up,addr=0 \
-drive file=./disk1.img,format=raw,if=none,id=nvme1 \
-device nvme,drive=nvme1,bus=sw0_down0,serial=1 \
-device xio3130-downstream,id=sw0_down1,chassis=1,slot=1,bus=sw0_up,addr=1 \
-device xio3130-downstream,id=sw0_down2,chassis=1,slot=2,bus=sw0_up,addr=2 \
-device e1000e,bus=sw0_down2
Results in:
PHB#0002:00:00.0 [ROOT] 1014 04c1 R:00 C:060400 B:01..05 SLOT=pcie.2
PHB#0002:01:00.0 [SWUP] 104c 8232 R:02 C:060400 B:02..05 SLOT=sw0_up
PHB#0002:02:00.0 [SWDN] 104c 8233 R:01 C:060400 B:03..03 SLOT=sw0_down0
PHB#0002:03:00.0 [EP ] 8086 5845 R:02 C:010802 ( mass-storage) LOC_CODE=sw0_down0
PHB#0002:02:01.0 [SWDN] 104c 8233 R:01 C:060400 B:04..04 SLOT=sw0_down1
PHB#0002:02:02.0 [SWDN] 104c 8233 R:01 C:060400 B:05..05 SLOT=sw0_down2
PHB#0002:05:00.0 [EP ] 8086 10d3 R:00 C:020000 ( ethernet) LOC_CODE=sw0_down2
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Add a slot table to our QEMU platform file to allow testing slot
functions and so that we have the basic infrastructure in place. The
slot names are the bus names that Qemu assigns to the subordiate bus of the
root port (i.e. where actual devices should go).
Devices can be added under a specific phb by specifying that bus. E.g.
-drive file=./disk1.img,format=raw,if=none,id=nvme0 \
-device nvme,drive=nvme0,bus=pcie.1
Places an NVMe device under the root port of PHB0001.
The six slots here will cover each of the six PHBs that exist in the
default P9 model. The P8 model has three (since that's what a Venice
has), but the extra slots shouldn't cause any problems.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Add a helper for adding builtin devices to a switch slot table and use
the VA_ARGS macro hacks to allow initialising other struct members (such
as the child pointer) to the ST_PLUGGABLE() and ST_BUILTIN() macros.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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