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2017-09-15core: make is_rodata test-friendlyOliver O'Halloran1-3/+10
Add a dummy is_rodata() implementation for use inside test code. Currently we don't need to make this actually check if the given pointer is actually read-only, but someone might want it to work properly in the future. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15core/pci-slots: Move slot-label construction to a helperOliver O'Halloran1-0/+3
Move this out of the astbmc specific part into a generic helper. This allows us to use it more commonly. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15core/pcie-slots: Make dynamic slot creation genericOliver O'Halloran1-0/+3
astbmc has some code to handle devices that are behind a "slot" on a riser card that can't be added to the static slot tables for a system. We probably want to use this code outside the slot table handling so move it somewhere generic and rework it so slot table specifics aren't buried inside it. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15core/pci-dt-slot: Represent PCIe slots in the devicetreeOliver O'Halloran1-0/+7
In P9 we get information about the physical PCIe slot topology through the HDAT. As a rule we never directly consume the HDAT inside of Skiboot and we always parse and incorporate the data from HDAT into the Skiboot device tree. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> [stewart@linux.vnet.ibm.com: add (C) header] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12phb4: Make link retries a #defineMichael Neuling1-0/+1
Make link retries a #define rather than open coding it in the PHB4 init code. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12pci: Make pci_wait_crs() globalMichael Neuling1-0/+1
We are going need pci_wait_crs() in the PHB4 code so make it global. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12phb4: Remove stable retriesMichael Neuling2-2/+0
This code was never used (since retries is set to 0), it's not very useful and it makes the code harder to read. So lets just remove it. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12npu2: Enable recoverable data link (no-stall) interruptsSam Bobroff1-0/+10
Allow the NPU2 to trigger "recoverable data link" interrupts. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Acked-By: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Ensure pressure relief interrupts are disabledBenjamin Herrenschmidt1-0/+1
We don't use them and we hijack the VP field with their configuration to store the EQ reference, so make sure the kernel or guest can't turn them back on by doing MMIO writes to ACK# Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12npu2: Implement FLRReza Arbab1-0/+1
Add basic handling of FLR (function level reset) by porting the changes from commit b74841db759d ("npu: Implement FLR") to npu2. The only difference for npu2 is that we track the reset state explicitly with a link flag instead of inferring it from dev->procedure_{status,number,step,data}. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Cc: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12npu2: Add npu2_clear_link_flag()Reza Arbab1-0/+1
Add a complement to npu2_set_link_flag(). Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-04capi: POWER9 DD2 updateChristophe Lombard1-0/+4
The CAPI initialization sequence has been updated in DD2. This patch adapts to the changes, retaining compatibility with DD1. The patch includes some changes to DD1 fix-ups as well. Tests performed on some of the old/new hardware. Some CAPP registers are initialized through the initfile p9.cxa.scom as the CAPP FIR, Transport Control and Snoop control registers. The following features will be added soon: - CAPP recovery. - Credit setup for Non Blocking Write + force quiesce. - Disable CAPI mode. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-04DT: Add ibm,firmware-versions nodeVasant Hegde2-0/+4
In P8, hostboot provides mini device tree. It contains /ibm,firmware-versions node which has various firmware component version details. In P9, OPAL is building device tree. This patch adds support to parse VERSION section of PNOR and create "/ibm,firmware-versions" device tree node. Sample output: /sys/firmware/devicetree/base/ibm,firmware-versions # lsprop . occ "6a00709" skiboot "v5.7-rc1-p344fb62" buildroot "2017.02.2-7-g23118ce" capp-ucode "9c73e9f" petitboot "v1.4.3-p98b6d83" sbe "02021c6" open-power "witherspoon-v1.17-128-gf1b53c7-dirty" .... .... Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Mukesh Ojha <mukesh02@linux.vnet.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-24bump skiboot size from 3 to 4MB, reduce heap by 1MBStewart Smith1-2/+2
GCOV enabled builds with modern GCC are getting bigger. At some point we're going to have to go do something sensible, but even on our larger systems we're not *that* close to running out of heap that this would be a problem. HEAP is now 12MB rather than 13MB. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-22vas: Set FIRs according to workbookMichael Neuling1-7/+3
This sets the FIR, FIR mask and FIR action registers according to VAS workbook v1.20. It also renames them to make it clear what they are. Without this any VAS error will checkstop the machine, rather than potentially be recoverable. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-21pci: Track whether a PCI device is a virtual functionRussell Currey1-0/+1
This can be checked from config space, but we will need to know this when restoring the PCI topology, and it is not always safe to access config space during this period. Signed-off-by: Russell Currey <ruscur@russell.cc> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-21vas: Set mmio enable bits in DD2Sukadev Bhattiprolu1-0/+3
POWER9 DD2 added some new "enable" bits that must be set for VAS to work. These bits were unused in DD1. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Acked-By: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-11phb4: Enhanced PCIe training tracingMichael Neuling1-0/+17
This add more details to the PCI training tracing (aka Rick Mata mode). It enables the PCIe Link Training and Status State Machine (LTSSM) tracing and details on speed and link width. Output now looks like this when enabled (via nvram): [ 1.096995141,3] PHB#0000[0:0]: TRACE:0x0000001101000000 0ms GEN1:x16:detect [ 1.102849137,3] PHB#0000[0:0]: TRACE:0x0000102101000000 11ms presence GEN1:x16:polling [ 1.104341838,3] PHB#0000[0:0]: TRACE:0x0000182101000000 14ms training GEN1:x16:polling [ 1.104357444,3] PHB#0000[0:0]: TRACE:0x00001c5101000000 14ms training GEN1:x16:recovery [ 1.104580394,3] PHB#0000[0:0]: TRACE:0x00001c5103000000 14ms training GEN3:x16:recovery [ 1.123259359,3] PHB#0000[0:0]: TRACE:0x00001c5104000000 51ms training GEN4:x16:recovery [ 1.141737656,3] PHB#0000[0:0]: TRACE:0x0000144104000000 87ms presence GEN4:x16:L0 [ 1.141752318,3] PHB#0000[0:0]: TRACE:0x0000154904000000 87ms trained GEN4:x16:L0 [ 1.141757964,3] PHB#0000[0:0]: TRACE: Link trained. [ 1.096834019,3] PHB#0001[0:1]: TRACE:0x0000001101000000 0ms GEN1:x16:detect [ 1.105578525,3] PHB#0001[0:1]: TRACE:0x0000102101000000 17ms presence GEN1:x16:polling [ 1.112763075,3] PHB#0001[0:1]: TRACE:0x0000183101000000 31ms training GEN1:x16:config [ 1.112778956,3] PHB#0001[0:1]: TRACE:0x00001c5081000000 31ms training GEN1:x08:recovery [ 1.113002083,3] PHB#0001[0:1]: TRACE:0x00001c5083000000 31ms training GEN3:x08:recovery [ 1.114833873,3] PHB#0001[0:1]: TRACE:0x0000144083000000 35ms presence GEN3:x08:L0 [ 1.114848832,3] PHB#0001[0:1]: TRACE:0x0000154883000000 35ms trained GEN3:x08:L0 [ 1.114854650,3] PHB#0001[0:1]: TRACE: Link trained. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04xscom: Add xscom_write_mask() functionAlistair Popple1-1/+1
It is common for xscom registers to only contain specific bit fields that need to be modified without altering the rest of the register. This adds a convenience function to perform xscom read-modify-write operations under a mask. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04npu2: Set the XTS config2 registerReza Arbab1-0/+1
POWER9 DD2 has added a new bit we'd like to set: "XTS_CONFIG2_NO_FLUSH_ENA: if enabled, allows MMIO ATSDs to suppress the flush" This has passed sanity tests with 4.12 kernels, which are capable of exercising this capability. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Cc: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04npu2: Adjust content of the NTL BARReza Arbab1-2/+4
Reflect the changed NTL BAR layout in POWER9 DD2. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Cc: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04npu2: Adjust content of the GENID BARReza Arbab1-2/+3
Reflect the changed GENID BAR layout in POWER9 DD2. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04npu2: Add NPU2_GPU1_MEM_BARReza Arbab1-0/+1
POWER9 DD2 has added a second GPU memory BAR. Use it, but continue to program things the old way on DD1 systems. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Cc: Alistair Popple <alistair@popple.id.au> Cc: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04npu2: Fix indirect SCOM addressesReza Arbab1-2/+4
Change these values for POWER9 DD2, but keep backwards compatibility. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04phb4: Enable PCI peer-to-peerFrederic Barrat3-1/+17
P9 supports PCI peer-to-peer: a PCI device can write directly to the mmio space of another PCI device. It completely by-passes the CPU. It requires some configuration on the PHBs involved: 1. on the initiating side, the address for the read/write operation is in the mmio space of the target, i.e. well outside the range normally allowed. So we disable range-checking on the TVT entry in bypass mode. 2. on the target side, we need to explicitly enable p2p by setting a bit in a configuration register. It has the side-effect of reserving an outbound (as seen from the CPU) store queue for p2p. Therefore we only enable p2p on the PHBs using it, as we don't want to waste the resource if we don't have to. P9 supports p2p mmio writes. Reads are currently only supported if the two devices are under the same PHB but that is expected to change in the future, and it raises questions about intermediate switches configuration, so we report an error for the time being. The patch adds a new OPAL call to allow the OS to declare a p2p (initiator, target) pair. Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01NX: Add P9 NX support for gzip compression engineHaren Myneni1-0/+1
Power 9 introduces NX gzip compression engine. This patch adds gzip compression support in NX. Virtual Accelerator Switch (VAS) is used to access NX gzip engine and the channel configuration will be done with the receive FIFO. So RxFIFO address, logical partition ID (lpid), process ID (pid) and thread ID (tid) are used to configure RxFIFO. P9 NX supports high and normal priority FIFOS. Skiboot configures User Mode Access Control (UMAC) noitify match register with these values and also enables other registers to enable / disable the engine. Creates the following device-tree entries to provide RxFIFO address, RxFIFO size, Fifo priority, lpid, pid and tid values so that kernel can drive P9 NX gzip engine. The following nodes are located under an xscom node: /xscom@<xscom_addr>/nx@<nx_addr> /ibm,gzip-high-fifo : High priority gzip RxFIFO /ibm,gzip-normal-fifo : Normal priority gzip RxFIFO Each RxFIFO node contains: compatible : ibm,p9-nx-gzip priority : High or Normal rx-fifo-address : RxFIFO address rx-fifo-size : RxFIFO size lpid : 0xfff (1's for 12 bits in UMAC notify match register) pid : gzip coprocessor type tid : counter for gzip Signed-off-by: Haren Myneni <haren@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01NX: Add P9 NX support for 842 compression engineHaren Myneni1-0/+5
This patch adds changes needed for 842 compression engine on power 9. Virtual Accelerator Switch (VAS) is used to access NX 842 engine on P9 and the channel setup will be done with receive FIFO. So RxFIFO address, logical partition ID (lpid), process ID (pid) and thread ID (tid) are used for this setup. p9 NX supports high and normal priority FIFOs. skiboot is not involved to process data with 842 engine, but configures User Mode Access Control (UMAC) noitify match register with these values and export them to kernel with device-tree entries. Also configure registers to setup and enable / disable the engine with the appropriate registers. Creates the following device-tree entries to provide RxFIFO address, RxFIFO size, Fifo priority, lpid, pid and tid values so that kernel can drive P9 NX 842 engine. The following nodes are located under an xscom node: /xscom@<xscom_addr>/nx@<nx_addr> /ibm,842-high-fifo : High priority 842 RxFIFO /ibm,842-normal-fifo : Normal priority 842 RxFIFO Each RxFIFO node contains: compatible : ibm,p9-nx-842 priority : High or Normal rx-fifo-address : RxFIFO address rx-fifo-size : RXFIFO size lpid : 0xfff (1's for 12 bits set in UMAC notify match register) pid : 842 coprocessor type tid : Counter for 842 Signed-off-by: Haren Myneni <haren@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01NX: Organize NX compression code to include 842 and gzip supportHaren Myneni1-3/+15
P9 NX also supports gzip compression. So this patch creates nx-compress.c and reorg nx-842.c code so that common functions that are needed for both 842 and gzip compression will be moved in to nx-compress.c. This patch does not change the actual functionality. Signed-off-by: Haren Myneni <hmyneni@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01NX: Add P9 NX register defines for 842 / gzip enginesHaren Myneni1-2/+86
This patch adds defines for 842 / gzip engine registers introduced on P9 NX and their bit values. Some of these register defines will not be used in skiboot right now, but added to sync with existing defines in nx.h. Signed-off-by: Haren Myneni <hmyneni@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01vas: Define vas_get_wcbs_bar interfaceSukadev Bhattiprolu1-0/+1
Implement the function vas_get_wcbs_bar() that returns the Window Context Backing store address register. NX driver uses this function to initialize its UMAC Send WC register. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01vas: Define vas_get_hvwc_mmio_bar interfaceSukadev Bhattiprolu1-0/+1
The nest accelerator (NX) will need this interface to initialize its UMAC MMIO BAR. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01vas: Initialize VAS registersSukadev Bhattiprolu1-0/+3
Initialize the VAS registers on each of instance that we discover. Initializing VAS involves writing either pre-defined values or allocated addresses to appropriate SCOM addresses. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: update phys_map_get API usage] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01vas: Define macros of constants and register fieldsSukadev Bhattiprolu1-0/+142
Define macros for the various Base Address Regions and Register fields that are needed by VAS. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01Define helpers to extract P9 node/chip idsSukadev Bhattiprolu1-0/+4
VAS needs the node and chip ids to compute the "paste address" of a window. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28sensors: occ: Add support to clear sensor groupsShilpasri G Bhat2-1/+5
Adds a generic API to clear sensor groups. OCC inband sensor groups such as CSM, Profiler and Job Scheduler can be cleared using this API. It will clear the min/max of all sensors belonging to OCC sensor groups. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28sensors: occ: Add support for OCC inband sensorsShilpasri G Bhat2-0/+5
Add support to parse and export OCC inband sensors which are copied by OCC to main memory in P9. Each OCC writes three buffers which includes one names buffer for sensor meta data and two buffers for sensor readings. While OCC writes to one buffer the sensor values can be read from the other buffer. The sensors are updated every 100ms. This patch adds power, temperature, current and voltage sensors to /ibm,opal/sensors device-tree node which can be exported by the ibmpowernv-hwmon driver in Linux. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28psr: occ: Add support to change power-shifting-ratioShilpasri G Bhat2-1/+49
Add support to set the CPU-GPU power shifting ratio which is used by the OCC power capping algorithm. PSR value of 100 takes all power away from CPU first and a PSR value of 0 caps GPU first. Documentation enhanced by Stewart Smith. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28powercap: occ: Add a generic powercap frameworkShilpasri G Bhat2-1/+46
This patch adds a generic powercap framework and exports OCC powercap sensors using which system powercap can be set inband through OPAL-OCC command-response interface. Documentation for powercap enhanced by Stewart Smith. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28opal-msg: Increase the max-async completion count by max chips possibleShilpasri G Bhat1-1/+1
OPAL-OCC command-response framework will also use async requests. So bump up the max-async completion requests to accommodate maximum number of chips possible. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28occ: Add support for OPAL-OCC command/response interfaceShilpasri G Bhat1-0/+1
This patch adds support for a shared memory based command/response interface between OCC and OPAL. In HOMER, there is an OPAL command buffer and an OCC response buffer which is used to send inband commands to OCC. The OPAL-OCC command/response sequence is as follows: 1. Check if both 'OCC Progress' bit in OCC response flag and 'Cmd Ready' bit in OPAL command flag are set to zero. If yes then proceed with below steps to send a command to OCC. 2. Write the command value, request ID and command specific data to the OPAL command buffer. 3. Clear the response flag and set the 'Cmd Ready' bit in OPAL command flag to indicate command is ready. 4. OCC will poll the command flag every 4ms to check if 'Cmd Ready' bit is set by OPAL. If the bit is set then OCC will set the 'OCC Progress' bit. 5. OCC will process the command and write the response to the OCC response buffer and set the 'Rsp Ready' bit in the response flag and sends an interrupt. 8. OPAL will receive the interrupt and queue the response to the host. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Reviewed-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28phb4: Be more conservative on link presence timeoutMichael Neuling1-1/+1
In this patch we tuned our link timing to be more agressive: cf960e2884 phb4: Improve reset and link training timing Cards should take only 32ms but unfortunately we've seen some take up to 440ms. Hence bump our timer up to 1000ms. This can hurt boot times on systems where slots indicate a hotplug status but no electrical link is present (which we've seen). Since we have to wait 1 second between PERST and touching config space anyway, it shouldn't hurt too much. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-25phb4: Add link training trace modeMichael Neuling1-0/+1
Add a mode to PHB4 to trace training process closely. This activates as soon as PERST is deasserted and produces human readable output of the process. This may increase training times since it duplicates some of the training code. This code has it's own simple checks for fence and timeout but will fall through to the default training code once done. Output produced, looks like the "TRACE:" lines below: [ 3.410799664,7] PHB#0001[0:1]: FRESET: Starts [ 3.410802000,7] PHB#0001[0:1]: FRESET: Prepare for link down [ 3.410806624,7] PHB#0001[0:1]: FRESET: Assert skipped [ 3.410808848,7] PHB#0001[0:1]: FRESET: Deassert [ 3.410812176,3] PHB#0001[0:1]: TRACE: 0x0000000101000000 0ms [ 3.417170176,3] PHB#0001[0:1]: TRACE: 0x0000100101000000 12ms presence [ 3.436289104,3] PHB#0001[0:1]: TRACE: 0x0000180101000000 49ms training [ 3.436373312,3] PHB#0001[0:1]: TRACE: 0x00001d0811000000 49ms trained [ 3.436420752,3] PHB#0001[0:1]: TRACE: Link trained. [ 3.436967856,7] PHB#0001[0:1]: LINK: Start polling [ 3.437482240,7] PHB#0001[0:1]: LINK: Electrical link detected [ 3.437996864,7] PHB#0001[0:1]: LINK: Link is up [ 4.438000048,7] PHB#0001[0:1]: LINK: Link is stable Enabled via nvram using: nvram -p ibm,skiboot --update-config pci-tracing=true Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-25phb4: Improve reset and link training timingMichael Neuling2-2/+5
This improves PHB reset and link training timing. Justifications and reasons are included in the patch. Polling frequencies are decreased from 100ms to 10ms. Added is a new state called PHB4_SLOT_LINK_STABLE which is now needed since the link training can be so fast that we touch config space too quickly (PCIe spec requires 1 second between PERST de-assert and device config space reads). We use this new state to sanity check the PHB and link before moving onto the PCI bus scan, where we no longer recover from these error conditions. Also added is simplified documentation of the PHB reset and training flow. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-17skiboot: Fix comment around OPAL_IMC_COUNTERS_ enumMadhavan Srinivasan1-1/+1
Fixes: 7801be0fcf2a2 ('skiboot: Add opal calls to init/start/stop IMC devices) Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-13IPMI: Move MAX_IPMI_SENSORS macro to ipmi.hVasant Hegde1-0/+2
..so that it can be used in other places as well. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-13phb4: Rework retries so we can do more than oneMichael Neuling1-0/+1
This reworks the pci link training retry code so that we can do more than one retry. This will now also print an error if a link fails to train. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-12xive: Enable memory backing of queuesBenjamin Herrenschmidt1-0/+6
This dedicates 6x64k pages of memory permanently for the XIVE to use for internal queue overflow. This allows the XIVE to deal with some corner cases where the internal queues might prove insufficient. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-12xive: Properly get rid of donated indirect pages during resetBenjamin Herrenschmidt1-0/+7
Otherwise they keep being used accross kexec causing memory corruption in subsequent kernels once KVM has been used. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-30cpu: Cleanup AMR and IAMR when re-initializing CPUsBenjamin Herrenschmidt1-0/+2
There's a bug in current Linux kernels leaving crap in those registers accross kexec and not sanitizing them on boot. This breaks kexec under some circumstances (such as booting a hash kernel from a radix one on P9 DD2.0). The long term fix is in Linux, but this workaround is a reasonable way of "sanitizing" those SPRs when Linux calls opal_reinit_cpus() and shouldn't have adverse effects. We could also use that same mechanism to cleanup other things as well such as restoring some other SPRs to their default value in the future. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-30phb4: Fix number of index bits in IODA tablesBenjamin Herrenschmidt1-1/+1
On PHB4 the number of index bits in the IODA table address register was bumped to 10 bits to accomodate for 1024 MSIs and 1024 TVEs (DD2). However our macro only defined the field to be 9 bits, thus causing "interesting" behaviours on some systems. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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