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AgeCommit message (Expand)AuthorFilesLines
2021-08-06phb4: Cleanup PEC config discovery in CAPI modeFrederic Barrat1-3/+7
2021-08-06phb5: Workaround for PCI bug HW551382Frederic Barrat1-1/+1
2021-08-06phb5: Add register inits specific to Gen5Frederic Barrat1-2/+4
2021-08-06hw/phb5: Update PHB numbering to allow for virtual PHBsFrederic Barrat1-1/+1
2021-08-06xive/p10: Tune max_entries_in_modified when split_mode is onCédric Le Goater1-0/+1
2021-08-06xive/p10: Activate has_array when PQ_disable is availableCédric Le Goater1-0/+2
2021-08-06xive/p10: Activate split mode for PHB ESBs when PQ_disable is availableCédric Le Goater1-0/+5
2021-08-06xive/p10: Introduce a new OPAL_XIVE_IRQ_STORE_EOI2 flagCédric Le Goater1-0/+1
2021-08-06xive/p10: Add automatic Context Save and Restore supportCédric Le Goater2-1/+8
2021-08-06xive/p10: Configure XIVE for fused coresCédric Le Goater1-0/+12
2021-08-06xive/p10: Introduce new capability bitsCédric Le Goater2-1/+10
2021-08-06psi/p10: Introduce xive2_source_mask()Cédric Le Goater1-0/+2
2021-08-06hw/phb5: Add support for 'Address-Based Interrupt Trigger' modeCédric Le Goater1-0/+2
2021-08-06hw/phb5: Add support for PQ offloadingCédric Le Goater2-0/+3
2021-08-06hw/phb5: Add initial supportJordan Niethe4-13/+26
2021-08-06psi/p10: Activate StoreEOICédric Le Goater1-0/+1
2021-08-06psi/p10: Activate 64K ESB pagesCédric Le Goater1-2/+3
2021-08-06xive/p10: Add a XIVE2 driverCédric Le Goater2-0/+578
2021-08-06hw/imc: Power10 supportAnju T Sudhakar1-0/+2
2021-08-06NX: Set VAS RMA write BAR register on P10Haren Myneni2-0/+4
2021-08-06hw/phys-map/p10: Add P10 MMIO mapAlistair Popple1-1/+5
2021-08-06phys/P10: Use topology index to get phys mappingVasant Hegde1-0/+3
2021-08-06hdat/spira: Add ibm, power10-vas-x string to VAS compatible propertyHaren Myneni1-2/+3
2021-08-06hdat/spira: Define ibm, primary-topology-index property per chipHaren Myneni1-0/+3
2021-08-06psi/p10: Activate P10 interruptsCédric Le Goater1-0/+7
2021-08-06p10: Workaround core recovery issueMichael Neuling1-0/+2
2021-08-06Initial POWER10 enablementNicholas Piggin6-15/+227
2021-07-19powercap: occ: Set occ_set_powercap as const attributePratik R. Sampat1-1/+1
2021-06-30hw/imc: Cleanup code to define scom addr for IMC at run timeAnju T Sudhakar1-2/+2
2021-06-30hw/p8-i2c: Add buses at runtimeOliver O'Halloran1-0/+3
2021-06-30hdat/i2c: Rework i2c device creationOliver O'Halloran1-0/+5
2021-06-30hw/p8-i2c: Add p8_i2c_find_bus_by_port()Oliver O'Halloran1-0/+3
2021-06-30i2c,trace: Add I2C operation trace eventsOliver O'Halloran2-8/+13
2021-06-30trace: Add nvram hack to use the old trace export behaviourOliver O'Halloran1-0/+1
2021-02-04phb4: Disable TCE cache line bufferFrederic Barrat1-0/+1
2020-12-15Revert "mowgli: Limit slot1 to Gen3 by default"LuluTHSu1-1/+0
2020-12-15hw/ocmb: Clear top bit from offset before searching addr rangeVasant Hegde1-0/+6
2020-11-02phb4: Finish removing P9 DD1 workaround on LSIsCédric Le Goater1-1/+0
2020-11-02mowgli: Limit slot1 to Gen3 by defaultLuluTHSu1-0/+1
2020-10-01skiboot.lds.S: Move BSS start up a bit to accommodate a larger .dataOliver O'Halloran1-2/+2
2020-10-01secvar/backend: add edk2 derived key updates processingNayna Jain1-0/+1
2020-10-01secvar/storage: add secvar storage driver for pnor-based p9Eric Richter1-0/+1
2020-10-01core/flash.c: add SECBOOT read and write supportClaudio Carvalho1-0/+3
2020-10-01secvar: change backend hook interface to take in bank referencesNayna Jain1-5/+17
2020-10-01include/secvar.h: add .lockdown() hook to secvar storage driverEric Richter1-3/+4
2020-08-07Add POWER9 Cumulus processor PVR typeVaidyanathan Srinivasan1-0/+15
2020-08-07cpu: Make cpu_get_core_index() return the fused core numberBenjamin Herrenschmidt2-0/+11
2020-08-07cpu: Keep track of the "ec_primary" in big core moreBenjamin Herrenschmidt1-0/+1
2020-08-07chip: Fix pir_to_thread_id for fused coresBenjamin Herrenschmidt1-0/+7
2020-08-07xive: Set the fused core mode properlyBenjamin Herrenschmidt1-0/+1
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