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2017-06-07phb4: Activate shared PCI slot on witherspoonFrederic Barrat3-0/+15
Witherspoon systems come with a 'shared' PCI slot: physically, it looks like a x16 slot, but it's actually two x8 slots connected to two PHBs of two different chips. Taking advantage of it requires some logic on the PCI adapter. Only the Mellanox CX5 adapter is known to support it at the time of this writing. This patch enables support for the shared slot on witherspoon if a x16 adapter is detected. Each x8 slot has a presence bit, so both bits need to be set for the activation to take place. Slot sharing is activated through a gpio. Note that there's no easy way to be sure that the card is indeed a shared-slot compatible PCI adapter and not a normal x16 card. Plugging a normal x16 adapter on the shared slot should be avoided on witherspoon, as the link won't train on the second slot, resulting in a timeout and a longer boot time. Only the first slot is usable and the x16 adapter will end up using only half the lines. If the PCI card plugged on the physical slot is only x8 (or less), then the presence bit of the second slot is not set, so this patch does nothing. The x8 (or less) adapter should work like on any other physical slot. Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: re-org code, move into platform file] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-06Improve cpu_idle when PM is disabledNicholas Piggin1-6/+2
Split cpu_idle() into cpu_idle_delay() and cpu_idle_job() rather than requesting the idle type as a function argument. Have those functions provide a default polling (non-PM) implentation which spin at the lowest SMT priority. This moves all the decrementer delay code into the CPU idle code rather than the caller. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-06cpu: Introduce smt_lowest()Nicholas Piggin2-2/+3
Recent CPUs have introduced a lower SMT priority. This uses the Linux pattern of executing priority nops in descending order to get a simple portable way to put the CPU into lowest SMT priority. Introduce smt_lowest() and use it in place of smt_very_low and smt_low ; smt_very_low sequences. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-06phb4: Block D-state power management on direct slotsBenjamin Herrenschmidt1-0/+3
As current revisions of PHB4 don't properly handle the resulting L1 link transition. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-06pci: Make handling of config filters genericBenjamin Herrenschmidt1-1/+3
Move phb3_pcicfg_filter() to pci.c, rename it to pci_handle_cfg_filters() Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-06pci: Add bitmap to know if a pci device has cfg reg filtersBenjamin Herrenschmidt1-0/+4
This avoids doing a search through the list of all devices on every config space access to every device under a PHB. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-06npu2: Fix npu2_{read,write}_4b()Reza Arbab1-2/+2
When writing or reading 4-byte values, we need to use the upper half of the 64-bit SCOM register. Fix npu2_{read,write}_4b() and their callers to use uint32_t, and appropriately shift the value being written or returned. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-06p8-i2c: occ: Add support for OCC to use I2C enginesShilpasri G Bhat1-0/+3
This patch adds support to share the I2C engines with host and OCC. OCC uses I2C engines to read DIMM temperatures and to communicate with GPU. OCC Flag register is used for locking between host and OCC. Host requests for the bus by setting a bit in OCC Flag register. OCC sends an interrupt to indicate the change in ownership. Originally-from: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: Pretty heavily rework logic, including fixing bus owner change and separating out occ lock from sensor cache] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-06hw/npu2.c: Add memory coherence directory programmingAlistair Popple1-0/+5
The memory coherence directory (MCD) needs to know which system memory addresses belong to the GPU. This amounts to setting a BAR and a size in the MCD to cover the addresses assigned to each of the GPUs. To ease assignment we assume GPUs are assigned memory in a contiguous block per chip. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-06prd: Implement firmware side of opaque PRD channelJeremy Kerr1-0/+37
This change introduces the firmware side of the opaque HBRT <--> OPAL message channel. We define a base message format to be shared with HBRT (in include/prd-fw-msg.h), and allow firmware requests and responses to be sent over this channel. We don't currently have any notifications defined, so have nothing to do for firmware_notify() at this stage. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> CC: Daniel M Crowell <dcrowell@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-06opal-prd: Add firmware_request & firmware_notify implementationsJeremy Kerr1-0/+16
This change adds the implementation of firmware_request() and firmware_notify(). To do this, we need to add a message queue, so that we can properly handle out-of-order messages coming from firmware. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-31core/pci: Rename pci_slot_op poll to run_smMichael Neuling1-1/+1
This renames the "poll" op to "run_sm" (short for run state machine). I think this is a better name since the function does a bunch of things like reseting the slot. Also it avoids confusion with the "poll_link" op which does something different (and can even be called from run_sm). No functional change. Signed-off-by: Michael Neuling <mikey@neuling.org> Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-26libflash/mbox-flash: Update to V2 of the protocolCyril Bur1-0/+11
Updated version 2 of the protocol can be found at: https://github.com/openbmc/mboxbridge/blob/master/Documentation/mbox_protocol.md This commit changes mbox-flash such that it will preferentially talk version 2 to any capable daemon but still remain capable of talking to v1 daemons. Version two changes some of the command definitions for increased consistency and usability. Version two includes more attention bits - these are now dealt with at a simple level. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Acked-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-26hw/lpc-mbox: Use message registers for interruptsCyril Bur1-2/+2
Currently the BMC raises the interrupt using the BMC control register. It does so on all accesses to the 16 'data' registers meaning that when the BMC only wants to set the ATTN (on which we have interrupts enabled) bit we will also get a control register based interrupt. The solution here is to mask that interrupt permanantly and enable interrupts on the protocol defined 'response' data byte. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-26mem_region: Add HW-only memory resevationsOliver O'Halloran1-0/+1
Add a new type of memory reservation that indicates a memory region is only used by hardware and should not be touched by software. This is needed for the in-memory tracing buffers. These reservations have the "no-map" property which indicates that the host kernel should not setup any virtual address mappings that cover this range, unless of course a device driver does so explicitly. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-26mem_region: rename HW_RESERVE to FW_RESERVEOliver O'Halloran1-2/+2
Currently all existing reservations are made by hostboot itself or on behalf of some other part of system firmware (e.g. the OCCs). We want to add a "true" hardware reservation type that should not be touched by the host OS. To prepare for that this patch renames the existing reservation type to refect it's actual usage. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-26fsp/tpo: Provide support for disabling TPO alarmVaibhav Jain1-0/+1
This patch adds support for disabling a preconfigured Timed-Power-On(TPO) alarm on FSP based systems. Presently once a TPO alarm is configured from the kernel it will be triggered even if its subsequently disabled. With this patch a TPO alarm can be disabled by passing y_m_d==hr_min==0 to fsp_opal_tpo_write(). A branch is added to the function to handle this case by sending FSP_CMD_TPO_DISABLE message to the FSP instead of usual FSP_CMD_TPO_WRITE message. The kernel is expected to call opal_tpo_write() with y_m_d==hr_min==0 to request opal to disable TPO alarm. Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-16phys map: Add missing NPU user regs regionMichael Neuling1-0/+1
We don't use this region currrently but we should add for completeness. Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-10phb4: Migrate BAR assignment to phys_map_get()Michael Neuling1-2/+0
Keeps existing addresses. No functional change. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-10Add global physical memory mapMichael Neuling1-0/+63
This adds a global map for allocating physical memory address. This centralises physical memory space allocations into one location rather than spread through, PHB, XIVE, NX etc. This adds a new call phys_map_get() which takes a chip, type and index and returns a address and size for the region to be used. An error in a call to this function crashes skiboot. This is done since bogus calls here are going to be hit by developers not users and they need to be fixed. Currently only P9 is implemented but other chips should be easy to add. On P9 BARs are generally set by skiboot. On P8 this was done by hostboot so this is not needed there. This just adds the infrastructure. User (PHB4, XIVE etc) will be migrated in subsequent patches. Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-10phb4: Enforce root complex config space size of 2048Michael Neuling1-0/+1
The root complex config space size on PHB4 is 2048. This patch sets that size and enforces it when trying to read/write the config space in the root complex. Without this someone reading the config space via /sysfs in linux will cause an EEH on the PHB. If too high, reads returns 1s and writes are silently dropped. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-10npu2: Fix BAR mapping for multiple chipsAlistair Popple2-16/+14
NPU2 BARs were being assigned and tracked with a global static array. This worked fine when there was only a single chip/NPU2 in the system however multiple chips results in the a shared data structure for BAR management which results in multiple chips getting assigned the same BAR addresses and other incorrect sharing of BAR properties. This patch splits the static and dynamic BAR configuration and stores the dynamic configuration in the per-NPU2 data structure. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-10FSP: Notify FSP of Platform Log ID after Host Initiated Reset ReloadStewart Smith2-5/+14
Trigging a Host Initiated Reset (when the host detects the FSP has gone out to lunch and should be rebooted), would cause "Unknown Command" messages to appear in the OPAL log. This patch implements those messages How to trigger FSP RR(HIR): $ putmemproc 300000f8 0x00000000deadbeef s1 k0:n0:s0:p00 ecmd_ppc putmemproc 300000f8 0x00000000deadbeef Log showing unknown command: / # cat /sys/firmware/opal/msglog | grep -i ,3 [ 110.232114723,3] FSP: fsp_trigger_reset() entry [ 188.431793837,3] FSP #0: Link down, starting R&R [ 464.109239162,3] FSP #0: Got XUP with no pending message ! [ 466.340598554,3] FSP-DPO: Unknown command 0xce0900 [ 466.340600126,3] FSP: Unhandled message ce0900 The message we need to handle is "Get PLID after host initiated FipS reset/reload". When the FSP comes back from HIR, it asks "hey, so, which error log explains why you rebooted me?". So, we tell it. Reported-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-04-28xive+phb4: Fix exposing trigger page to LinuxBenjamin Herrenschmidt1-5/+9
We currently don't expose the trigger page of MSIs to Linux which breaks re-sending of a queued one. To fix that properly we need to understand out a subtle API complication: - The "internal" XIVE_SRC_TRIGGER_PAGE indicates that a trigger page is supported, whether it's the same page as the EOI page or not. - The "external" OPAL_XIVE_IRQ_TRIGGER_PAGE indicates that a *separate* trigger page exists. To know if triggers are supported the caller should simply check if a valid (non-0) value is returned in "out_trig_page" of opal_xive_get_irq_info(). So PHB4 must set XIVE_SRC_TRIGGER_PAGE for MSIs and the xive code needs to do the "right" thing for setting whether OPAL_XIVE_IRQ_TRIGGER_PAGE should be set or not. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-04-27nx: Add POWER9 DARN supportMichael Neuling2-0/+12
This sets up the per chip RNG MMIO BAR and points the per core DARN BAR at it. This is needed on P9 to enabled the DARN instruction (otherwise it'll cause a xstop). This includes a minor rework of some #defines to abstract MMIO definitions. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-04-27console: Set log level from nvramMichael Neuling1-1/+3
This adds two new nvram options to set the console log level for the driver/uart and in memory. These are called log-level-memory and log-level-driver. These are only set once we have nvram inited. To set them you do: nvram -p ibm,skiboot --update-config log-level-memory=9 nvram -p ibm,skiboot --update-config log-level-driver=9 You can also use the named versions of emerg, alert, crit, err, warning, notice, printf, info, debug, trace or insane. ie. nvram -p ibm,skiboot --update-config log-level-driver=insane Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-04-27npu: Implement FLRAlexey Kardashevskiy1-0/+1
As the comment in npu_dev_populate_pcie_cap() says, "We should support FLR" and the NPU device advertises its support. However, when the kernel issues FLR, skiboot does nothing which leaves NPU in a state which does not allow to use NV links again after GPU was reset. This adds basic handling of FLR (function level reset). This does not update hreset/freset handlers as they are not going to be called under any circumstance - EEH is not supported for NPU and the kernel won't issue OPAL reset otherwise. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-04-19phb4: Implement diag dataRussell Currey1-2/+69
Implement PHB4 diagnostic data, similar to PHB3. There are a few registers that have changed, but everything is largely the same. Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Michael Neuling <mikey@neuling.org>
2017-04-19phb4: Expand and clean up register definitionsRussell Currey1-9/+121
Add some missing register definitions, delete some duplicates and put things in order. Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Michael Neuling <mikey@neuling.org>
2017-04-19interrupts: Add an "irq_for_each_source" iteratorBenjamin Herrenschmidt1-0/+6
This will be used by subsequent XIVE reset improvements Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org>
2017-04-12occ/irq: Fix SCOM address and irq reasons for P9 OCCShilpasri G Bhat1-2/+5
This patch fixes the SCOM address for OCC_MISC register which is used for OCC interupts. In P9, OCC sends an interrupt to notify change in the shared memory like throttle status. This patch handles this interrupt reason. Originally-from: Michael Neuling <mikey@neuling.org> Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org>
2017-04-07device: add dt_find_by_name_addrOliver O'Halloran1-0/+5
Adds two helper functions that allow device nodes to be found via their name and unit address. One will take an integer address and format it to a hex string while the other looks up the unit based a user supplied string. This is handy in a few places inside the HDAT parser. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-04-05hdat: Add model-name property for OpenPower systemVasant Hegde1-1/+1
Lets add model-name property for OpenPower system as well. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-31hw/phb3: Adjust ECRC on root port dynamicallyGavin Shan1-0/+1
The issue was reported by Mark: the Samsung NVMe adapter is lost when it's connected to PMC 8546 PCIe switch, until ECRC is disabled on the root port. Actually, we found similar issue prevously when Broadcom adapter is connected to same part of PCIe switch and it was fixed by commit 60ce59ccd0e9 ("hw/phb3: Disable ECRC on Broadcom adapter behind PMC switch"). Unfortunately, the commit doesn't fix the Samsung NVMe adapter lost issue. This fixes the issues by disable ECRC generation/check on root port when PMC 8546 PCIe switch ports are found. This can be extended for other PCIe switches or endpoints in future: Each PHB maintains the count of PCI devices (PMC 8546 PCIe switch ports currently) which require to disable ECRC on root port. The ECRC functionality is enabled when first PMC 8546 switch port is probed and disabled when last PMC 8546 switch port is destroyed (in PCI hot remove scenario). Except PHB's reinitialization after complete reset, the ECRC on root port is untouched. Reported-by: Mark E Schreiter <markes@us.ibm.com> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Tested-by: Mark E Schreiter <markes@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-31core/pci: Add phb->ops->device_removeGavin Shan1-0/+1
This adds another PHB callback (device_remove()), corresponding to device_init(). With it, the PHB3 layer can receive notification upon PCI topology changes. This functionality will be used by the subsequent patches. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-30SLW: Add init for power9 power managementAkshay Adiga1-0/+6
This patch adds new function to init core for power9 power management. SPECIAL_WKUP_* SCOM registers, if set, can hold the cores from going into idle states. Hence, clear PPM_SPECIAL_WKUP_HYP_REG scom register for each core during init. (This init are not required for MAMBO) Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-30npu2: Add hardware link training proceduresAlistair Popple2-1/+15
Unlike other system buses the NVLink2 links need to be trained at runtime as training requires interaction from the GPU device drivers. This patch implements the required training procedures for NVLink2, which are different than the NVLink1 equivalents. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-30npu2: Add OPAL calls for nvlink2 address translation servicesAlistair Popple1-1/+4
Adds three OPAL calls for interacting with NPU2 devices: opal_npu_init_context, opal_npu_destroy_context and opal_npu_map_lpar. These are used to setup and configure address translation services (ATS) for a process/partition on a given NVLink2 device. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-30npu2: Allocate GPU memory and describe it in the dtReza Arbab1-0/+2
Allocate memory for the GPU vidmem aperture and create "memory@" dt nodes to describe GPU memory with a phandle in each pointing to the emulated PCI device. Also provide the compressed 47-bit device address in "ibm,device-tgt-addr". Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-30Introduce NPU2 supportAlistair Popple3-0/+154
NVLink2 is a new feature introduced on POWER9 systems. It is an evolution of of the NVLink1 feature included in POWER8+ systems but adds several new features including support for GPU address translation using the Nest MMU and cache coherence. Similar to NVLink1 the functionality is exposed to the OS as a series of virtual PCIe devices. However the actual hardware interfaces are significantly different which limits the amount of common code that can be shared between implementations in the firmware. This patch adds basic hardware initialisation and exposure of the virtual NVLink2 PCIe devices to the running OS. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-30npu2: Add npu2 register definitionsAlistair Popple1-0/+431
NPU2 registers are split up into a series of stacks and blocks. This adds definitions and register offset calculation macros for all of the register stacks/blocks in preparation for NPU2. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-29phb3/4: Set max link speed via nvramMichael Neuling1-0/+2
This adds an nvram parameter pcie-max-link-speed to configure the max speed of the pcie link. This can be set from the petitboot prompt using: nvram -p ibm,skiboot --update-config pcie-max-link-speed=4 This takes preference over anything set in the device tree and is global to all PHBs. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-24xscom: Add indirect form 1 scomsMichael Neuling1-0/+1
Add code to perform indirect form 1 scoms. POWER8 does form 0 only. POWER9 adds form 1. The form is determined from the address only. Hardware only allows writes for form 1. Only hostboot uses these scoms during IPL, so they are unused by skiboot currently. Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-20hw/phb3: disable CAPI mode during complete resetAndrew Donnellan1-4/+5
When fast rebooting or kexec-ing a system with a PHB in CAPI mode, we need to return the PHB to regular PCIe mode. In order to do this, we have to reset a bunch of registers to their pre-CAPI-mode state. However, doing this while there is traffic going over the PCI link is dangerous and will generally cause a checkstop. As such, we want to do this while the PHB is fenced. Conveniently, during a complete reset we force a PHB fence, so this is a good opportunity to disable CAPI mode. When doing a complete reset, if the PHB is in CAPI mode, execute a sequence of SCOMs to reset PHB-related registers back to their regular, PCIe mode values. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-16xive: Add opal_xive_sync() to sync IRQ sources and queuesBenjamin Herrenschmidt1-0/+7
For now support two sync options, source and target queue, we'll add sync'ing the presentation layer later. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-16hmi: Print CAPP FIR information when handling CAPP malfunction alertsAndrew Donnellan1-2/+5
When diagnosing or debugging CAPP errors, it's rather useful to have the CAPP FIR, which often provides very helpful information. Print the CAPP FIR to the log when we handle a Malfunction Alert HMI for a CAPP error. Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-16hw/fsp: Do not queue SP and SPCN class messages during reset/reloadAnanth N Mavinakayanahalli1-0/+1
During FSP R/R, the FSP is inaccessible and will lose state. Messages to the FSP are generally queued for sending later. It does seem like the FSP fails to process any subseuqent messages of certain classes (SP info -- ipmi) if it receives queued mbox messages it isn't expecting. In certain other cases (sensors), the FSP driver returns a default code (async completion) even though there is no known bound from the time of this error return to the actual data being available. The kernel driver keeps waiting leading to soft-lockup on the host side. Mitigate both these (known) cases by returning OPAL_BUSY so the host driver knows to retry later. With this change, the sensors command works fine when the FSP comes back. This version also resolves the remaining IPMI issues Signed-off-by: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com> Tested-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-09xive: Sync HW when moving interrupts aroundBenjamin Herrenschmidt1-0/+7
For now sync all queues, ensure any interrupt routed at the old queue has reached memory. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-07hdat: Parse BMC nodes much earlierOliver O'Halloran1-0/+1
This moves the parsing of the BMC and LPC details to the start of the HDAT parsing. This allows us to enable the Skiboot log console earlier so we can get debug output while parsing the rest of the HDAT. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-07System reset IPI facility and Mambo implementationNicholas Piggin1-1/+2
Add an opal call OPAL_SIGNAL_SYSTEM_RESET which allows system reset exceptions to be raised on other CPUs and act as an NMI IPI. There is an initial simple Mambo implementation, but allowances are made for a more complex hardware implementation. This API is based on the POWER8 implementation from Alistair Popple. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [stewart@linux.vnet.ibm.com: minor RST fix] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>