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2017-11-30nvram: Fix 'missing' nvram on FSP systems.Cyril Bur2-1/+2
commit ba4d46fdd9eb ("console: Set log level from nvram") wants to read from NVRAM rather early. This works fine on BMC based systems as nvram_init() is actually synchronous. This is not true for FSP systems and it turns out that the query for the console log level simply queries blank nvram. The simple fix is to wait for the NVRAM read to complete before performing any query. Unfortunately it turns out that the fsp-nvram code does not inform the generic NVRAM layer when the read is complete, rather, it must be prompted to do so. This patch addresses both these problems. This patch adds a check before the first read of the NVRAM (for the console log level) that the read has completed. The fsp-nvram code has been updated to inform the generic layer as soon as the read completes. The old prompt to the fsp-nvram code has been removed but a check to ensure that the NVRAM has been loaded remains. It is conservative but if the NVRAM is not done loading before the host is booted it will not have an nvram device-tree node which means it won't be able to access the NVRAM at all, ever, even after the NVRAM has loaded. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-28xive: Implement "single escalation" featureBenjamin Herrenschmidt1-7/+8
This adds a new VP flag to control the new DD2.0 "single escalation" feature. This feature allows us to have a single escalation interrupt per VP instead of one per queue. It works by hijacking queue 7 (which is this no longer usable when that is enabled) and exploiting two new hardware bits that will: - Make the normal queues (0..6) escalate unconditionally thus ignoring the ESe bits. - Route the above escalations to queue 7 - Have queue 7 silently escalate without notification Thus the escalation of queue 7 becomes the one escalation interrupt for all the other queues. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-28xive: Define API for single-escalation VP modeBenjamin Herrenschmidt1-0/+1
This mode allows all queues of a VP to use the same escalation interrupt, at the cost of losing priority 7. This adds the definition and documentation of the API, the implementation will come next. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-27core/bitmap: fix bitmap iteration limit corruptionNicholas Piggin1-2/+2
The bitmap iterators did not reduce the number of bits to scan when searching for the next bit, which would result in them overruning their bitmap. These are only used in one place, in xive reset, and the effect is that the xive reset code will keep zeroing memory until it reaches a block of memory of MAX_EQ_COUNT >> 3 bits in length, all zeroes. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-21npu2: Print bdfn in NPU2DEV* logging macrosReza Arbab1-3/+8
Revise the NPU2DEV{DBG,INF,ERR} logging macros to include the device's bdfn. It's useful to know exactly which link we're referring to. For instance, instead of [ 234.044921238,6] NPU6: Starting procedure reset_ntl [ 234.048578101,6] NPU6: Starting procedure reset_ntl [ 234.051049676,6] NPU6: Starting procedure reset_ntl [ 234.053503542,6] NPU6: Starting procedure reset_ntl [ 234.057182864,6] NPU6: Starting procedure reset_ntl [ 234.059666137,6] NPU6: Starting procedure reset_ntl we'll get [ 234.044921238,6] NPU6:0:0.0 Starting procedure reset_ntl [ 234.048578101,6] NPU6:0:0.1 Starting procedure reset_ntl [ 234.051049676,6] NPU6:0:0.2 Starting procedure reset_ntl [ 234.053503542,6] NPU6:0:1.0 Starting procedure reset_ntl [ 234.057182864,6] NPU6:0:1.1 Starting procedure reset_ntl [ 234.059666137,6] NPU6:0:1.2 Starting procedure reset_ntl Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-21pci: Track peers of slotsRussell Currey1-0/+1
Witherspoon introduced a new concept where one physical slot is shared between two PHBs. Making a slot aware of its peer enables syncing between them where necessary. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-20core/direct-controls: add function to read core gated stateRobert Lippert1-0/+1
Change-Id: Ib534503f2528de4d8b1633d9859ae9ff5d010f98 Signed-off-by: Robert Lippert <rlippert@google.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-20sensors: dts: Assert special wakeup on idle cores while reading temperatureShilpasri G Bhat2-1/+15
In P9, when a core enters a stop state, its clocks will be stopped to save power and hence we will not be able to perform a scom operation to read the DTS temperature sensor. Hence, assert a special wakeup on cores that have entered a stop state in order to successfully complete the scom operation. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> [rlippert@google.com: Clear special wakeup only when it succeeds] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-20p8-i2c: Limit number of retry attemptsOliver O'Halloran1-0/+1
Current we will attempt to start an I2C transaction until it succeeds. In the event that the OCC does not release the lock on an I2C bus this results in an async token being held forever and the kernel thread that started the transaction will block forever while waiting for an async completion message. Fix this by limiting the number of attempts to start the transaction. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-19npu2: Remove unused npu2_dev struct membersAndrew Donnellan1-3/+0
There's a few members of struct npu2_dev that are completely unused. Remove them. Cc: Alistair Popple <alistair@popple.id.au> Cc: Reza Arbab <arbab@linux.vnet.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Acked-by: Reza Arbab <arbab@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-15Revert "npu2: hw-procedures: Enable low power mode"Reza Arbab1-6/+0
As it turns out, low power mode is not yet ready for prime time. We shouldn't write the low power config register until it is. This reverts commit a05054c53a37850a2118d01fcf6669ebb10d1a33. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-15npu2: Move to new GPU memory mapMichael Neuling3-0/+7
There are three different ways we configure the MCD and memory map. 1) Old way (current way) Skiboot configures the MCD and puts GPUs at 4TB and below 2) New way with MCD Hostboot configures the MCD and skiboot puts GPU at 4TB and above 3) New way without MCD No one configures the MCD and skiboot puts GPU at 4TB and below The patch keeps option 1 and adds options 2 and 3. The different configurations are detected using certain scoms (see patch). Option 1 will go away eventually as it's a configuration that can cause xstops or data integrity problems. We are keeping it around to support existing hostboot. Option 2 supports only 4 GPUs and 512GB of memory per socket. Option 3 supports 6 GPUs and 4TB of memory but may have some performance impact. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-15phys-map: Rename GPU_MEM to GPU_MEM_4T_DOWNMichael Neuling1-1/+1
This map is soon to be replaced, but we are going to keep it around for a little while so that we support older hostboot firmware. Rename it for now. Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-15npu2: Refactor BAR setting codeMichael Neuling1-1/+2
This refactors the BAR setting code to make it clearer and handle a larger range of BAR addresses. This is needed as we are about to move the GPU to a physical address that is currently not supported by this code. This change derives group and chip sections of the BAR from the base address rather than the chip_id now. mem sel is also derived from the base address, rather than assuming 0. No functional change. Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-15npu2: Create npu2_write_mcd()Michael Neuling1-0/+3
This code is replicated, so let's put it in a function. Also add some cleanups. No functional change. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-13npu2: hw-procedures: Add phy_rx_clock_sel()Reza Arbab1-0/+1
Change the RX clk mux control to be done by software instead of HW. This avoids glitches caused by changing the mux setting. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Reviewed-By: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-13npu2: Add npu2_write_mask_4b()Reza Arbab1-0/+1
Add a 4-byte version of npu2_write_mask(). Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Reviewed-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-09xive: Update inits for DD2.0Benjamin Herrenschmidt1-5/+20
This updates some inits based on information from the HW designers. This includes enabling some new DD2.0 features that we don't yet exploit. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-09npu2: hw-procedures: Enable low power modeReza Arbab1-0/+6
Add a procedure which sets the NTL low power config register. To actually enter low power mode, a corresponding change must be present in the GPU device driver. The link will not enter low power mode unless both sides agree, which means this change is safe to make independently. It should have no forward or backward dependencies on other components. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-09capi: update ci store buffers and dma enginesChristophe Lombard1-0/+5
The number of read (APC type traffic) and mmio store (MSG type traffic) resources assigned to the CAPP is controlled by the CAPP control register. According to the type of CAPI cards present on the server, we have to configure differently the CAPP messages and the DMA read engines given to the CAPP for use. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Acked-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-29asm/head: initialize preferred DSCR valueNicholas Piggin1-0/+1
POWER7/8 use DSCR=0. POWER9 preferred value has "stride-N" enabled. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-23phb4: Escalate freeze to fence to avoid checkstopMichael Neuling1-0/+4
Freeze events such as MMIO loads can cause the PHB to lose it's limited powerbus credits. If all credits are used and a further MMIO will cause a checkstop. To work around this, we escalate the troublesome freeze events to a fence. The fence will cause a full PHB reset which resets the powerbus credits and avoids the checkstop. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-16cpu: Add OPAL_REINIT_CPUS_TM_SUSPEND_DISABLEDMichael Ellerman1-0/+2
Add a new CPU reinit flag, "TM Suspend Disabled", which requests that CPUs be configured so that TM (Transactional Memory) suspend mode is disabled. Currently this always fails, because skiboot has no way to query the state. A future hostboot change will add a mechanism for skiboot to determine the status and return an appropriate error code. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-15hw/imc: Use ARRAY_SIZE instead of static macroMadhavan Srinivasan1-2/+0
disable_unavailable_units() loops through nest_pmus array to filter out the unsupported nest units from the imc catalog dtb. Current code use a static macro ('MAX_NEST_UNITS') for array limit, instead use ARRAY_SIZE. This will avoid updates to static macro when updating the nest_pmus array. Fixes: 712837cedca06 ('skiboot/imc: Update the nest_pmus array with occ/gpe microcode uav updates') Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-11FSP: Disable PSI link whenever FSP tells OPAL about impending R/RVasant Hegde1-1/+0
Commit 42d5d047 fixed scenario where DPO has been initiated, but FSP went into reset before the CEC power down came in. But this is generic issue that can happen in normal shutdown path as well. Hence disable PSI link as soon as we detect FSP impending R/R. CC: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com> CC: Stewart Smith <stewart@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-10pci-iov: free memory across fast-rebootStewart Smith1-2/+7
pci_set_cap needs a callback to free data and we need to call that when we're doing __pci_reset() We also need to free pcrf entries. In the future, __pci_reset() and pci_remove_bus() need to come together to be one canonical place on how to free a PCI device rather than the two we have now. This patch *purely* focuses on the problem of not leaking memory across fast-reboot. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-02i2c: Move tpm i2c wrapper code into coreAndrew Donnellan1-0/+5
The TPM code has a wrapper around the main i2c API to allow synchronous use. Move it into core/i2c.c so it can be used by other possible users. In particular, a future patch will use this to drive OpenCAPI device resets during boot time. Cc: Claudio Carvalho <cclaudio@linux.vnet.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-28cpu: idle POWER9 power management implementationNicholas Piggin2-1/+34
Add pm idle support to POWER9. IPIs are implemented with doorbells. POWER9 can use the EC=ESL=0 (lite) stop when sreset is not available. EC=ESL=1 state with RL=3 is enabled when we have a sreset wakeup. Deep idle states are not implemented. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-28cpu: idle split pm enable into sreset and ipi componentsNicholas Piggin1-2/+6
pm idle requires the system reset vector and IPI facilities before it can be enabled. Split these out and manage them individually. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-28cpu: idle move the minimum PM latency into the idle codeNicholas Piggin1-1/+1
The caller isn't in a position to know about PM heuristics, so move the minimum timeout before power managmeent into the cpu idle call. There is no functional change. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-27skiboot/imc: Fix the core_imc_event_maskAnju T Sudhakar1-1/+1
CORE_IMC_EVENT_MASK is a scom that contains bits to control event sampling for different machine state for core imc. The current event-mask setting sample events only on host kernel (hypervisor) and host userspace. Patch to enable the sampling of events in other machine states (like guest kernel and guest userspace). Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-20core: POWER9 implement OPAL_SIGNAL_SYSTEM_RESETNicholas Piggin3-0/+26
This implements OPAL_SIGNAL_SYSTEM_RESET, using scom registers to quiesce the target thread and raise a system reset exception on it. It has been tested on DD2 with stop0 ESL=0 and ESL=1 shallow power saving modes. DD1 is not implemented because it is sufficiently different as to make support difficult. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [stewart@linux.vnet.ibm.com: fixup hdat_to_dt test] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19SLW: Add support for p9_stop_apiAkshay Adiga1-0/+163
p9_stop_api's are used to set SPR state on a core wakeup form a deeper low power state. p9_stop_api uses low level platform formware and self-restore microcode to restore the sprs to requested values. Code is taken from : https://github.com/open-power/hostboot/tree/master/src/import/chips/p9/procedures/utils/stopreg Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15core: make is_rodata test-friendlyOliver O'Halloran1-3/+10
Add a dummy is_rodata() implementation for use inside test code. Currently we don't need to make this actually check if the given pointer is actually read-only, but someone might want it to work properly in the future. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15core/pci-slots: Move slot-label construction to a helperOliver O'Halloran1-0/+3
Move this out of the astbmc specific part into a generic helper. This allows us to use it more commonly. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15core/pcie-slots: Make dynamic slot creation genericOliver O'Halloran1-0/+3
astbmc has some code to handle devices that are behind a "slot" on a riser card that can't be added to the static slot tables for a system. We probably want to use this code outside the slot table handling so move it somewhere generic and rework it so slot table specifics aren't buried inside it. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15core/pci-dt-slot: Represent PCIe slots in the devicetreeOliver O'Halloran1-0/+7
In P9 we get information about the physical PCIe slot topology through the HDAT. As a rule we never directly consume the HDAT inside of Skiboot and we always parse and incorporate the data from HDAT into the Skiboot device tree. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> [stewart@linux.vnet.ibm.com: add (C) header] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12phb4: Make link retries a #defineMichael Neuling1-0/+1
Make link retries a #define rather than open coding it in the PHB4 init code. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12pci: Make pci_wait_crs() globalMichael Neuling1-0/+1
We are going need pci_wait_crs() in the PHB4 code so make it global. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12phb4: Remove stable retriesMichael Neuling2-2/+0
This code was never used (since retries is set to 0), it's not very useful and it makes the code harder to read. So lets just remove it. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12npu2: Enable recoverable data link (no-stall) interruptsSam Bobroff1-0/+10
Allow the NPU2 to trigger "recoverable data link" interrupts. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Acked-By: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Ensure pressure relief interrupts are disabledBenjamin Herrenschmidt1-0/+1
We don't use them and we hijack the VP field with their configuration to store the EQ reference, so make sure the kernel or guest can't turn them back on by doing MMIO writes to ACK# Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12npu2: Implement FLRReza Arbab1-0/+1
Add basic handling of FLR (function level reset) by porting the changes from commit b74841db759d ("npu: Implement FLR") to npu2. The only difference for npu2 is that we track the reset state explicitly with a link flag instead of inferring it from dev->procedure_{status,number,step,data}. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Cc: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12npu2: Add npu2_clear_link_flag()Reza Arbab1-0/+1
Add a complement to npu2_set_link_flag(). Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-04capi: POWER9 DD2 updateChristophe Lombard1-0/+4
The CAPI initialization sequence has been updated in DD2. This patch adapts to the changes, retaining compatibility with DD1. The patch includes some changes to DD1 fix-ups as well. Tests performed on some of the old/new hardware. Some CAPP registers are initialized through the initfile p9.cxa.scom as the CAPP FIR, Transport Control and Snoop control registers. The following features will be added soon: - CAPP recovery. - Credit setup for Non Blocking Write + force quiesce. - Disable CAPI mode. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-04DT: Add ibm,firmware-versions nodeVasant Hegde2-0/+4
In P8, hostboot provides mini device tree. It contains /ibm,firmware-versions node which has various firmware component version details. In P9, OPAL is building device tree. This patch adds support to parse VERSION section of PNOR and create "/ibm,firmware-versions" device tree node. Sample output: /sys/firmware/devicetree/base/ibm,firmware-versions # lsprop . occ "6a00709" skiboot "v5.7-rc1-p344fb62" buildroot "2017.02.2-7-g23118ce" capp-ucode "9c73e9f" petitboot "v1.4.3-p98b6d83" sbe "02021c6" open-power "witherspoon-v1.17-128-gf1b53c7-dirty" .... .... Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Mukesh Ojha <mukesh02@linux.vnet.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-24bump skiboot size from 3 to 4MB, reduce heap by 1MBStewart Smith1-2/+2
GCOV enabled builds with modern GCC are getting bigger. At some point we're going to have to go do something sensible, but even on our larger systems we're not *that* close to running out of heap that this would be a problem. HEAP is now 12MB rather than 13MB. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-22vas: Set FIRs according to workbookMichael Neuling1-7/+3
This sets the FIR, FIR mask and FIR action registers according to VAS workbook v1.20. It also renames them to make it clear what they are. Without this any VAS error will checkstop the machine, rather than potentially be recoverable. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-21pci: Track whether a PCI device is a virtual functionRussell Currey1-0/+1
This can be checked from config space, but we will need to know this when restoring the PCI topology, and it is not always safe to access config space during this period. Signed-off-by: Russell Currey <ruscur@russell.cc> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-21vas: Set mmio enable bits in DD2Sukadev Bhattiprolu1-0/+3
POWER9 DD2 added some new "enable" bits that must be set for VAS to work. These bits were unused in DD1. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Acked-By: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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