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2018-04-03xive: disable store EOI supportCédric Le Goater1-0/+3
Hardware has limitations which would require to put a sync after each store EOI to make sure the MMIO operations that change the ESB state are ordered. This is a killer for performance and the PHBs do not support the sync. So remove the store EOI for the moment, until hardware is improved. Also, while we are at changing the XIVE source flags, let's fix the settings for the PHB4s which should follow these rules : - SHIFT_BUG for DD10 - STORE_EOI for DD20 and if enabled - TRIGGER_PAGE for DDx0 and if not STORE_EOI Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-30xive: Mask MMIO load/store to bad location FIRFrederic Barrat1-0/+2
For opencapi, the trigger page of an interrupt is mapped to user space. The intent is to write the page to raise an interrupt but there's nothing to prevent a user process from reading it, which has the infortunate consequence of checkstopping the system. Mask the FIR bit raised when an MMIO operation targets an invalid location. It's the recommendation from recent documentation and hostboot is expected to mask it at some point. In the meantime, let's play it safe. Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-11xive: Ensure VC informational FIRs are maskedBenjamin Herrenschmidt1-0/+6
Some HostBoot versions leave those as checkstop, they are harmless and can sometimes occur during normal operations. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Tested-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-03fast-reboot: bare bones fast reboot implementation for POWER9Nicholas Piggin1-0/+1
This is an initial fast reboot implementation for p9 which has only been tested on the Witherspoon platform, and without the use of NPUs, NX/VAS, etc. This has worked reasonably well so far, with no failures in about 100 reboots. It is hidden behind the traditional fast-reboot experimental nvram option, until more platforms and configurations are tested. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-28xive: Implement "single escalation" featureBenjamin Herrenschmidt1-7/+8
This adds a new VP flag to control the new DD2.0 "single escalation" feature. This feature allows us to have a single escalation interrupt per VP instead of one per queue. It works by hijacking queue 7 (which is this no longer usable when that is enabled) and exploiting two new hardware bits that will: - Make the normal queues (0..6) escalate unconditionally thus ignoring the ESe bits. - Route the above escalations to queue 7 - Have queue 7 silently escalate without notification Thus the escalation of queue 7 becomes the one escalation interrupt for all the other queues. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-09xive: Update inits for DD2.0Benjamin Herrenschmidt1-5/+20
This updates some inits based on information from the HW designers. This includes enabling some new DD2.0 features that we don't yet exploit. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Ensure pressure relief interrupts are disabledBenjamin Herrenschmidt1-0/+1
We don't use them and we hijack the VP field with their configuration to store the EQ reference, so make sure the kernel or guest can't turn them back on by doing MMIO writes to ACK# Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-12xive: Enable memory backing of queuesBenjamin Herrenschmidt1-0/+6
This dedicates 6x64k pages of memory permanently for the XIVE to use for internal queue overflow. This allows the XIVE to deal with some corner cases where the internal queues might prove insufficient. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-12xive: Properly get rid of donated indirect pages during resetBenjamin Herrenschmidt1-0/+7
Otherwise they keep being used accross kexec causing memory corruption in subsequent kernels once KVM has been used. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26xive: DD2.0 updatesBenjamin Herrenschmidt1-0/+7
Add support for StoreEOI, fix StoreEOI MMIO offset in ESB page, and other cleanups Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-04-28xive+phb4: Fix exposing trigger page to LinuxBenjamin Herrenschmidt1-5/+9
We currently don't expose the trigger page of MSIs to Linux which breaks re-sending of a queued one. To fix that properly we need to understand out a subtle API complication: - The "internal" XIVE_SRC_TRIGGER_PAGE indicates that a trigger page is supported, whether it's the same page as the EOI page or not. - The "external" OPAL_XIVE_IRQ_TRIGGER_PAGE indicates that a *separate* trigger page exists. To know if triggers are supported the caller should simply check if a valid (non-0) value is returned in "out_trig_page" of opal_xive_get_irq_info(). So PHB4 must set XIVE_SRC_TRIGGER_PAGE for MSIs and the xive code needs to do the "right" thing for setting whether OPAL_XIVE_IRQ_TRIGGER_PAGE should be set or not. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-09xive: Sync HW when moving interrupts aroundBenjamin Herrenschmidt1-0/+7
For now sync all queues, ensure any interrupt routed at the old queue has reached memory. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-02-07xive/psi/lpc: Handle proper clearing of LPC SerIRQ latch on DD1Benjamin Herrenschmidt1-0/+4
On DD1, the LPC SerIRQ are latched to 1 in HW but never back to 0, we need an explicit clear after running the handler. (Not before as they are level interrupts, they will be latched again if they are still pending). For now we do that in lpc_dispatch_ser_irqs() but that only works for interrupts routed to OPAL. In order to support routing LPC interrutps to Linux, we need a custom EOI handler that does the clearing of the latch before we do the EOI in the ESB. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-02-02xive: Set the FORCE_TM_LOCAL bit in CQ_PBI_CTLBenjamin Herrenschmidt1-0/+5
This bits saves the day if the special EX BARs happens to be misconfigured. There is no drawback to having it always set so let's do so. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-02-02xive: Fix definition of VC_SCRUB_OFFSETBenjamin Herrenschmidt1-1/+1
Off by one on one bit Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-01-05xive: Split the OPAL irq flags from the internal onesBenjamin Herrenschmidt1-5/+6
Some per-IRQ flags only have meaning inside OPAL, let's separate the two number spaces Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-01-05xive: Cleanup escalation PQ on queue changeBenjamin Herrenschmidt1-0/+4
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-01-05xive: Implement xive_resetBenjamin Herrenschmidt1-2/+4
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: fix build failure on older GCC - e.g. 4.8] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-01-05xive: Mark XIVE owned EQs with a specific flagBenjamin Herrenschmidt1-0/+2
This will allow us to recognize them later when doing a reset and avoid freeing them Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-01-05xive: Use an allocator for EQDsBenjamin Herrenschmidt1-0/+4
This adds a bitmap allocator for EQDs. They are allocated in groups of 8 naturally aligned. The VP structures associated with physical CPUs now have all 8 EQDs available though only one is provisioned and enabled. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-01-05xive: Break assumption that block ID == chip IDBenjamin Herrenschmidt1-0/+12
Add proper translation between the two. We still initialize them to the same thing but we will be able to change that easily if necessary (if the chip IDs become larger than 16 or if we decide to start using more than one block per chip). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-01-05xive/phb4: Handle bad ESB offsets in PHB4 DD1Benjamin Herrenschmidt1-0/+1
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-01-05xive: Implement cache watch and use it for EQsBenjamin Herrenschmidt1-0/+36
We need to do cache coherent updates of the EQs when modifying escalation interrupts. Use the cache watch facility for that. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-01-05xive: Add opal_xive_get_irq_info()Benjamin Herrenschmidt1-3/+4
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-01-05xive: Add support for escalation interruptsBenjamin Herrenschmidt1-0/+3
Escalation interrupts have their "IVE" entry buried inside of the EQ that shoots them which complicates matters. We want to expose them to the OS as normal interrupts, so we dedicate a bit in the interrupt number (outside the range supported by the OPAL emulation API) to differenciate them. The BlockID and Index in the interrupt number now refer to the source EQ. This is still missing proper cache management for them, which will come in a separate patch. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15xive: Provide a way to override some IPI sourcesBenjamin Herrenschmidt1-3/+5
Some devices such as NX or the NPU will use some of the XIVE provided IPIs for their own interrupts. Thus we need a way for those to provide a custom irq_source_ops for portions of the IPI space in order for them to provide their own attributes() and if needed, interrutps() callbacks. We achieve that by creating a second list of sources which can overlap the primary. The global stock of IPIs is registered by XIVE in the secondary list which is searched when no match is found in the primary. A new API xive_register_ipi_source() is provided for those devices to create an overlapping source structure in the primary list for a subset of the IPIs. Those IPIs must have been previously allocated using xive_alloc_ipi_irqs() Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15xive: Add helper to retrieve an IPI trigger portBenjamin Herrenschmidt1-0/+5
To be used by such things as VAS Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-08-11xive: Wrap irq_sources to provide standard set_xive/get_xiveBenjamin Herrenschmidt1-2/+9
All the source controllers use the standard XIVE mechanism for masking/unmasking and EOI, so there is no point having that logic duplicated. There are a few variations on how they are implemented but that can be handled using a few flags. So let's create a wrapper around irq_sources for a xive source and provide a new API for things like PHB4 to instanciate them This patch while at it also fixes the calculation of the source offset when setting up targetting information in the PHB4. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-07-08XIVE: Base XIVE support for OPAL XICS emulation callsBenjamin Herrenschmidt1-0/+378
This provides basic initialization of the XIVE along with some OPAL calls to emulate an old-style XICS which will initially be used by Linux for backward compatibility. The current implementation is limited to one priority and doesn't expose much to Linux for future exploitation mode yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: add (C) header, fix whitespace, missing breaks] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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