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2018-02-13ATTN: Enable flush instruction cache bit in HID registerVasant Hegde1-1/+1
In P9, we have to enable "flush the instruction cache" bit along with "attn instruction support" bit to trigger attention. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-03core/lock: Introduce atomic cmpxchg and implement try_lock with itNicholas Piggin1-0/+4
cmpxchg will be used in a subsequent change, and this reduces the amount of asm code. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [stewart: fix some ifdef __TEST__ foo to ensure unittests work] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-29asm/head: initialize preferred DSCR valueNicholas Piggin1-0/+1
POWER7/8 use DSCR=0. POWER9 preferred value has "stride-N" enabled. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-28cpu: idle POWER9 power management implementationNicholas Piggin1-0/+31
Add pm idle support to POWER9. IPIs are implemented with doorbells. POWER9 can use the EC=ESL=0 (lite) stop when sreset is not available. EC=ESL=1 state with RL=3 is enabled when we have a sreset wakeup. Deep idle states are not implemented. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-20core: POWER9 implement OPAL_SIGNAL_SYSTEM_RESETNicholas Piggin1-0/+15
This implements OPAL_SIGNAL_SYSTEM_RESET, using scom registers to quiesce the target thread and raise a system reset exception on it. It has been tested on DD2 with stop0 ESL=0 and ESL=1 shallow power saving modes. DD1 is not implemented because it is sufficiently different as to make support difficult. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [stewart@linux.vnet.ibm.com: fixup hdat_to_dt test] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-30cpu: Cleanup AMR and IAMR when re-initializing CPUsBenjamin Herrenschmidt1-0/+2
There's a bug in current Linux kernels leaving crap in those registers accross kexec and not sanitizing them on boot. This breaks kexec under some circumstances (such as booting a hash kernel from a radix one on P9 DD2.0). The long term fix is in Linux, but this workaround is a reasonable way of "sanitizing" those SPRs when Linux calls opal_reinit_cpus() and shouldn't have adverse effects. We could also use that same mechanism to cleanup other things as well such as restoring some other SPRs to their default value in the future. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26cpu: Support setting HID[RADIX] and set it by default on P9Benjamin Herrenschmidt1-0/+1
This adds new opal_reinit_cpus() flags to setup radix or hash mode in HID[8] on POWER9. By default HID[8] will be set. On P9 DD1.0, Linux will change it as needed. On P9 DD2.0 hash works in radix mode (radix is really "dual" mode) so KVM won't break and existing kernels will work. Newer kernels built for hash will call this to clear the HID bit and thus get the full size of the TLB as an optimization. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-06cpu: Introduce smt_lowest()Nicholas Piggin1-0/+2
Recent CPUs have introduced a lower SMT priority. This uses the Linux pattern of executing priority nops in descending order to get a simple portable way to put the CPU into lowest SMT priority. Introduce smt_lowest() and use it in place of smt_very_low and smt_low ; smt_very_low sequences. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-01-16Fix PIR mask for POWER9Michael Neuling1-1/+1
Fix typo in PIR mask for POWER9. Fixes booting multi-chip. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-10-17Fast reboot for P8Benjamin Herrenschmidt1-0/+1
This is an experimental patch that implements "Fast reboot" on P8 machines. The basic idea is that when the OS calls OPAL reboot, we gather all the threads in the system using a combination of patching the reset vector and soft-resetting them, then cleanup a few bits of hardware (we do re-probe PCIe for example), and reload & restart the bootloader. For Trusted Boot, this means we *add* measurements to the TPM, so you will get *different* PCR values as compared to a full IPL. This makes sense as if you want to be sure you are running something known then, well, do a full IPL as soft reset should never be trusted to clear any malicious code. This is very experimental and needs a lot of testing and also auditing code for other bits of HW that might need to be cleaned up. BenH TODO: I also need to check if we are properly PERST'ing PCI devices. This is partially based on old code I had to do that on P7. I only support it on P8 though as there are issues with the PSI interrupts on P7 that cannot be reliably solved. Even though this should be considered somewhat experimental, we've had a lot of success on a variety of machines. Dozens/hundreds of reboots across Tuleta, Garrison and Habanero. Currently, we've hidden it behind a NVRAM config option, which *is* liable to change in the future (to ensure that only those who know what they're doing enable it) You can enable the experimental support via nvram option: nvram -p ibm,skiboot --update-config experimental-fast-reset=feeling-lucky Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: hide behind nvram option, include Mambo fixes from Mikey] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-09-06core/init: ensure that HRMOR is zero at bootOliver O'Halloran1-0/+1
We have only ever supported running with HRMOR = 0. Having a non-zero HRMOR causes all real mode accesses to have the value of HRMOR bitwise ORed into the address that would have been accessed. This causes issues when accessing MMIO registers such as the XSCOMs. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-07-19Allow mtspr/mfspr to compile indepedantly of the optimization levelBalbir Singh1-2/+4
The compiler expects to see a constant value in the asm operations involving spr's. When compiling with -O0, spr is treated as a variable on stack when inline (this can be seen from the RTL). We do two things to fix the issue, we mark the functions as always_inline and we pass spr as a const so that the value is propagated as constants to the inline asm statement Tested with -O0 Signed-off-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-07-01cpu: supply ibm,dec-bits via devicetreeOliver O'Halloran1-0/+1
ISAv3 adds a mode to increase the size of the decrementer from 32 bits. The enlarged decrementer can be between 32 and 64 bits wide with the exact value being implementation dependent. This patch adds support for detecting the size of the large decrementer and populating each CPU node with the "ibm,dec-bits" property. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: rename enable_ld() to enable_large_dec()] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-05-10Add base POWER9 supportMichael Neuling1-0/+4
Add PVR detection, chip id and other misc bits for POWER9. POWER9 changes the location of the HILE and attn enable bits in the HID0 register, so add these definitions also. Signed-off-by: Michael Neuling <mikey@neuling.org> [stewart@linux.vnet.ibm.com: Fix Numbus typo, hdata_to_dt build fixes] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-05-10Abstract HILE and attn enable bit definitions for HID0Michael Neuling1-2/+2
Abstract HILE and attn enable bits definitions for HID0 in case these locations randomly change in future chip revisions. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-03-11Remove unused variablesMichael Neuling1-2/+0
These aren't used, so remove them. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-06-18Merge branch 'stable'Stewart Smith1-0/+1
2015-06-18Set proper value for RPR registerskiboot-5.0.4Benjamin Herrenschmidt1-0/+1
The value was provided by Dave Larson and is what pHyp uses Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-04-09Add Naples chip supportBenjamin Herrenschmidt1-0/+1
This adds the PVR and CFAM ID for the Naples chip. Otherwise treated as a Venice. This doesn't add the definitions for the new PHB revision yet Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-03-26opal: Handle TB residue and HDEC parity HMI errors on split core.Mahesh Salgaonkar1-0/+2
In case of split core, some of the Timer facility errors needs cleanup to be done before we proceed with the error recovery. Certain TB/HDEC errors leaves dirty data in timebase and HDEC registers, which need to cleared before we initiate clear_tb_errors through TFMR[24]. The cleanup has to be done by any one thread from core or subcore. In split core mode, it is required to clear the dirty data from TB/HDEC register by all subcores (active partitions) before we clear tb errors through TFMR[24]. The HMI recovery would fail even if one subcore do not cleanup the respective TB/HDEC register. Dirty data can be cleaned by writing zero's to TB/HDEC register. For un-split core, any one thread can do the cleanup. For split core, any one thread from each subcore can do the cleanup. Errors that required pre-recovery cleanup: - SPR_TFMR_TB_RESIDUE_ERR - SPR_TFMR_HDEC_PARITY_ERROR This patch implements pre-recovery steps to clean dirty data from TB/HDEC register for above mentioned timer facility errors. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-03-26opal: Recover from TFMR SPURR/PURR parity error.Mahesh Salgaonkar1-0/+2
Recovery process for SPURR/PURR parity error: - Set SPURR/PURR Register with valid value or zero - Reset TFMR SPURR/PURR parity error bit. To inject TFMR PURR parity error issue: $ putscom pu.ex 10013281 0004080000000000 -all To inject TFMR SPURR parity error issue: $ putscom pu.ex 10013281 0005080000000000 -all Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-03-26opal: Recover from TFMR DEC parity error.Mahesh Salgaonkar1-0/+1
Recovery process for TFMR DEC parity error: - Set DEC Register with all ones. - Reset TFMR DEC parity error bit. To inject TFMR DEC parity error issue: $ putscom pu.ex 10013281 0006080000000000 -all Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-03-26opal: Recover from TFMR HDEC parity error.Mahesh Salgaonkar1-0/+1
Recovery process for HDEC parity error: - Reset HDEC Register. - Reset TFMR HDEC parity error bit. To inject HDEC parity error issue: $ putscom pu.ex 10013281 0002080000000000 -all Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-02-19Change user-defined _MASK/_LSH to just maskDan Streetman1-20/+10
The last patch changed the SETFIELD() and GETFIELD() macros to automatically calculate the shift of a given mask, so manually specifying the shift is no longer needed. Additionally, any masks should have the _MASK suffix removed since the GETFIELD() and SETFIELD() operations expected to be passed the mask name without the _MASK suffix (and so either the mask name or the get/setfield call needs to have its mask name changed). Change all _MASK masks to remove the _MASK suffix, except for any places that leaving _MASK makes sense (e.g. already an existing define without _MASK suffix). Remove all _LSH defines, as they are no longer needed. Signed-off-by: Dan Streetman <ddstreet@ieee.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2014-07-02Initial commit of Open Source releaseBenjamin Herrenschmidt1-0/+318
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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