| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
Use Software Package Data Exchange (SPDX) to indicate license for each
file that is unique to skiboot.
At the same time, ensure the (C) who and years are correct.
See https://spdx.org/
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
[oliver: Added a few missing files]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
|
|
It's been a good long while since either OPAL POWER7 user touched a
machine, and even longer since they'd have been okay using an old
version rather than tracking master.
There's also been no testing of OPAL on POWER7 systems for an awfully
long time, so it's pretty safe to assume that it's very much bitrotted.
It also saves a whole 14kb of xz compressed payload space.
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Enthusiasticly-Acked-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
|
|
The read offset (4:11) in Receive FIFO control register is incremented
by FIFO size whenever CRB read by NX. But the index in RxFIFO has to
match with the corresponding entry in FIFO maintained by VAS in kernel.
VAS entry is reset to 0 when opening the receive window during driver
initialization. So when NX842 is reloaded or in kexec boot, possibility
of mismatch between RxFIFO control register and VAS entries in kernel.
It could cause CRB failure / timeout from NX.
This patch adds nx_coproc_init opal call for kernel to initialize
readOffset (4:11) and Queued (15:23) in RxFIFO control register.
Fixes: 3b3c5962f432 ("NX: Add P9 NX support for 842 compression engine")
CC: stable # v5.8+
Signed-off-by: Haren Myneni <haren@us.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
|
|
Power 9 introduces NX gzip compression engine. This patch adds gzip
compression support in NX. Virtual Accelerator Switch (VAS) is used to
access NX gzip engine and the channel configuration will be done with
the receive FIFO. So RxFIFO address, logical partition ID (lpid),
process ID (pid) and thread ID (tid) are used to configure RxFIFO.
P9 NX supports high and normal priority FIFOS. Skiboot configures User
Mode Access Control (UMAC) noitify match register with these values and
also enables other registers to enable / disable the engine.
Creates the following device-tree entries to provide RxFIFO address,
RxFIFO size, Fifo priority, lpid, pid and tid values so that kernel
can drive P9 NX gzip engine.
The following nodes are located under an xscom node:
/xscom@<xscom_addr>/nx@<nx_addr>
/ibm,gzip-high-fifo : High priority gzip RxFIFO
/ibm,gzip-normal-fifo : Normal priority gzip RxFIFO
Each RxFIFO node contains:
compatible : ibm,p9-nx-gzip
priority : High or Normal
rx-fifo-address : RxFIFO address
rx-fifo-size : RxFIFO size
lpid : 0xfff (1's for 12 bits in UMAC notify match
register)
pid : gzip coprocessor type
tid : counter for gzip
Signed-off-by: Haren Myneni <haren@us.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
This patch adds changes needed for 842 compression engine on power 9.
Virtual Accelerator Switch (VAS) is used to access NX 842 engine on P9
and the channel setup will be done with receive FIFO. So RxFIFO
address, logical partition ID (lpid), process ID (pid) and thread ID
(tid) are used for this setup. p9 NX supports high and normal priority
FIFOs. skiboot is not involved to process data with 842 engine, but
configures User Mode Access Control (UMAC) noitify match register with
these values and export them to kernel with device-tree entries.
Also configure registers to setup and enable / disable the engine with
the appropriate registers. Creates the following device-tree entries to
provide RxFIFO address, RxFIFO size, Fifo priority, lpid, pid and tid
values so that kernel can drive P9 NX 842 engine.
The following nodes are located under an xscom node:
/xscom@<xscom_addr>/nx@<nx_addr>
/ibm,842-high-fifo : High priority 842 RxFIFO
/ibm,842-normal-fifo : Normal priority 842 RxFIFO
Each RxFIFO node contains:
compatible : ibm,p9-nx-842
priority : High or Normal
rx-fifo-address : RxFIFO address
rx-fifo-size : RXFIFO size
lpid : 0xfff (1's for 12 bits set in UMAC notify
match register)
pid : 842 coprocessor type
tid : Counter for 842
Signed-off-by: Haren Myneni <haren@us.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
P9 NX also supports gzip compression. So this patch creates
nx-compress.c and reorg nx-842.c code so that common functions that are
needed for both 842 and gzip compression will be moved in to
nx-compress.c. This patch does not change the actual functionality.
Signed-off-by: Haren Myneni <hmyneni@us.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
This patch adds defines for 842 / gzip engine registers introduced on P9
NX and their bit values. Some of these register defines will not be used in
skiboot right now, but added to sync with existing defines in nx.h.
Signed-off-by: Haren Myneni <hmyneni@us.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
This only adds defines for various NX registers and their bit values. This
doesn't add any code that uses them, and it's possible skiboot won't need to
use any of these registers, as they're the error and status registers, which
will be monitored/handled from the FSP. So this patch isn't required to add;
I added all these while I still thought the kernel driver needed to handle
them, and I hate to just throw their definitions away ;-) If skiboot ever
does need to use any of the status or err registers, the definitions will
already be in place with this patch.
This patch shouldn't actually affect the compiled binary at all, since it's
only adding unused defines.
Signed-off-by: Dan Streetman <ddstreet@ieee.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
Set the NX crb input queues to be used by 842 only, by not reserving any input
queue slots for the sym or asym engines. This allows the maximum number of
842 crb requests to be queued up, to (hopefully) improve 842 performance.
This patch isn't critical, as the default is no extra input queue locations
for asym, and only 1 extra input queue location for sym, so this only takes
sym's extra location for use by 842.
There is 1 each dedicated input queue location for asym and sym (and 842), so
this patch won't prevent them from working if support is ever added for them.
Signed-off-by: Dan Streetman <ddstreet@ieee.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
Add NX config register values for P7+. Remove "P8" from all register
defines, where the define is common to P7+ and P8. For values new to P8
(specifically 842 prefeching), only enable on P8.
This should correctly setup the NX coprocessors on P7+ systems.
Signed-off-by: Dan Streetman <ddstreet@ieee.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
Add support for the 842 hw memory compression engine in the NX Coprocessor.
This moves the existing RNG support into its own nx-rng.c file, adds 842
support in a nx-842.c file, and creates a nx-crypto.c file to configure and
disable the crypto engines (which are not supported yet).
New nodes are created for each 842 engine found. This does not actually
process any of the data or drive the 842 engines, it only configures
registers to set up and enable/disable the engines appropriately, and
creates new nodes so the OS can drive the 842 engines.
Signed-off-by: Dan Streetman <ddstreet@ieee.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
|
|
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
