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2020-10-01skiboot.lds.S: Move BSS start up a bit to accommodate a larger .dataOliver O'Halloran1-2/+2
Witht addition of libtss and mbedtls the .data section now overlaps the start of the .bss section. Adding a few MB to the offset doesn't hurt. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-11core: interrupt markers for stack tracesNicholas Piggin1-1/+1
Use magic marker in the exception stack frame that is used by the unwinder to decode the interrupt type and NIA. The below example trace comes from a modified skiboot that uses virtual memory, but any interrupt type will appear similarly. CPU 0000 Backtrace: S: 0000000031c13580 R: 0000000030028210 .vm_dsi+0x360 S: 0000000031c13630 R: 000000003003b0dc .exception_entry+0x4fc S: 0000000031c13830 R: 0000000030001f4c exception_entry_foo+0x4 --- Interrupt 0x300 at 000000003002431c --- S: 0000000031c13b40 R: 000000003002430c .make_free.isra.0+0x110 S: 0000000031c13bd0 R: 0000000030025198 .mem_alloc+0x4a0 S: 0000000031c13c80 R: 0000000030028bac .__memalign+0x48 S: 0000000031c13d10 R: 0000000030028da4 .__zalloc+0x18 S: 0000000031c13d90 R: 000000003002fb34 .opal_init_msg+0x34 S: 0000000031c13e20 R: 00000000300234b4 .main_cpu_entry+0x61c S: 0000000031c13f00 R: 00000000300031b8 boot_entry+0x1b0 --- OPAL boot --- Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [oliver: the new stackentry fields made our test heaps too small] Signed-off-by: Oliver O'Halloran <oohall@gmail.com> fixup! core: interrupt markers for stack traces
2020-03-12Re-license IBM written files as Apache 2.0 OR GPLv2+Stewart Smith1-1/+1
SPDX makes it a simpler diff. I have audited the commit history of each file to ensure that they are exclusively authored by IBM and thus we have the right to relicense. The motivation behind this is twofold: 1) We want to enable experiments with coreboot, which is GPLv2 licensed 2) An upcoming firmware component wants to incorporate code from skiboot and code from the Linux kernel, which is GPLv2 licensed. I have gone through the IBM internal way of gaining approval for this. The following files are not exclusively authored by IBM, so are *not* included in this update (I will be seeking approval from contributors): core/direct-controls.c core/flash.c core/pcie-slot.c external/common/arch_flash_unknown.c external/common/rules.mk external/gard/Makefile external/gard/rules.mk external/opal-prd/Makefile external/pflash/Makefile external/xscom-utils/Makefile hdata/vpd.c hw/dts.c hw/ipmi/ipmi-watchdog.c hw/phb4.c include/cpu.h include/phb4.h include/platform.h libflash/libffs.c libstb/mbedtls/sha512.c libstb/mbedtls/sha512.h platforms/astbmc/barreleye.c platforms/astbmc/garrison.c platforms/astbmc/mihawk.c platforms/astbmc/nicole.c platforms/astbmc/p8dnu.c platforms/astbmc/p8dtu.c platforms/astbmc/p9dsu.c platforms/astbmc/vesnin.c platforms/rhesus/ec/config.h platforms/rhesus/ec/gpio.h platforms/rhesus/gpio.c platforms/rhesus/rhesus.c platforms/astbmc/talos.c platforms/astbmc/romulus.c Signed-off-by: Stewart Smith <stewart@linux.ibm.com> [oliver: fixed up the drift] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-16naca: move naca definition from asm to CNicholas Piggin1-0/+2
This results in the same layout and location of the naca and hv data structures. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-11Remove dead POWER7 codeNicholas Piggin1-1/+1
There are a number of proc_gen branches removed that are trivially dead code and comments that refer to P7. As well as those: - Oliver points out that add_xics_icps() must be unused on POWER8 because it asserts if number of threads > 4, so remove it. - Change 16b7ae641 ("Remove POWER7 and POWER7+ support") removed all references to opal_boot_trampoline, so remove that. - It also removed the only non-trival choose_bus implementation, so that is removed and its caller simplified. - Remove the paca code, later CPUs use pcia. Cc: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15MPIPL: Reserve memory to capture architected registers dataVasant Hegde1-1/+13
- Split SPIRAH memory to accommodate architected register ntuple. Today we have 1K memory for SPIRAH and it uses 288 bytes. Lets split this into two parts : SPIRAH (756 bytes) architected register memory (256 bytes) - Update SPIRAH architected register ntuple - Calculate memory required to capture architected registers data Ideally we should use HDAT provided data (proc_dump_area->thread_size). But we are not getting this data during boot. Hence lets reserve fixed memory for architected registers data collection. - Add architected registers destination memory to reserve-memory DT node. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15MPIPL: Define OPAL metadata areaVasant Hegde1-1/+7
We want to save some information (like crashing CPU PIR, kernel tags, etc) before triggering MPIPL. Post MPIPL we will use this information to retrieve dump metadata and create dump. MDRT table doesn't need 64K. Hence split MDRT table to accommodate metadata area. Finally define metadata structure. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15mem-map: Setup memory for MDRT tableVasant Hegde1-1/+7
Hostboot fills MDRT table after moving memory content from source to destination memory. And OPAL relies on this table to extract the dump. We have to make sure this table is intact. Hence define memory relative to SKIBOOT_BASE so that our relocation doesn't overwrite this memory. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15mem-map: Setup memory for MDDT tableVasant Hegde1-2/+6
Each entry in MDST and MDDT takes 16 bytes. With 1K we can have upto 64 entries. This is sufficient to support OPAL MPIPL (memory preserving IPL). Presently OPAL reserves 2K memory for MDST table. Lets split this into two region of 1K for MDST and MDDT table. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26SPDX-ify all skiboot codeStewart Smith1-15/+2
Use Software Package Data Exchange (SPDX) to indicate license for each file that is unique to skiboot. At the same time, ensure the (C) who and years are correct. See https://spdx.org/ Signed-off-by: Stewart Smith <stewart@linux.ibm.com> [oliver: Added a few missing files] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-06-04Remove POWER7 and POWER7+ supportStewart Smith1-4/+1
It's been a good long while since either OPAL POWER7 user touched a machine, and even longer since they'd have been okay using an old version rather than tracking master. There's also been no testing of OPAL on POWER7 systems for an awfully long time, so it's pretty safe to assume that it's very much bitrotted. It also saves a whole 14kb of xz compressed payload space. Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Enthusiasticly-Acked-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-05-21With new GCC comes larger GCOV binariesStewart Smith1-7/+9
So we need to change our heap size to make more room for data/bss without having to change where the console is or have more fun moving things about. Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-04-18core/opal: Emergency stack for re-entryNicholas Piggin1-4/+6
This detects OPAL being re-entered by the OS, and switches to an emergency stack if it was. This protects the firmware's main stack from re-entrancy and allows the OS to use NMI facilities for crash / debug functionality. Further nested re-entry will destroy the previous emergency stack and prevent returning, but those should be rare cases. This stack is sized at 16kB, which doubles the size of CPU stacks, so as not to introduce a regression in primary stack size. The 16kB stack originally had a 4kB machine check stack at the top, which was removed by 80eee1946 ("opal: Remove machine check interrupt patching in OPAL."). So it is possible the size could be tightened again, but that would require further analysis. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-03-27mem-map: Use a symbolic constant for exception vector sizeNicholas Piggin1-0/+5
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-24bump skiboot size from 3 to 4MB, reduce heap by 1MBStewart Smith1-2/+2
GCOV enabled builds with modern GCC are getting bigger. At some point we're going to have to go do something sensible, but even on our larger systems we're not *that* close to running out of heap that this would be a problem. HEAP is now 12MB rather than 13MB. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-04-01hdata: Initialize SPIRA-H structureVasant Hegde1-1/+4
Previous patch reduced reserved space in spira structure. Now its safe to reduce the memory for spira section from 2K to 1K. Create separate memory section with 1K size for SPIRA-H. Also initialize SPIRA-H. FSP makes use of this information to pass various boot time data (like SPIRA-S, etc) to host. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-05-15Add 2MB to skiboot heapStewart Smith1-9/+12
Rearrange memory map slightly, adding in an extra 2MB into skiboot heap. We lost 1MB of HEAP when allowing skiboot binary to be 2MB, and we were starting to get close to not having a lot of room to play with, especially on larger systems. With this patch: - on Tuleta, we now have 4,422,472 free in firmware-heap for runtime. - on Mambo, we have 13,094,080 free Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-05-15Make skiboot able to be 2MB rather than 1MBStewart Smith1-2/+2
When built with gcov, skiboot is >1MB (closer to 1.5MB) and there were a few assumptions about skiboot being <1MB. The biggest one was that when code got larger, we'd have the sbss section start in the middle of code, so that when we were going to relocate ourselves, we'd only get the first 1MB of skiboot relocated, which excluded the _DYNAMIC section, meaning that relocate() would not find the right sections. We also needed to not start writing over random parts of skiboot. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2014-10-30core: Add support for loading an external initramfsJeremy Kerr1-1/+4
Using the platform.load_resource interface, allow an external initramfs image to be passed to the kernel. We split the KERNEL_LOAD_BASE/KERNEL_LOAD_SIZE region in half, to allow space for the initramfs. Signed-off-by: Jeremy Kerr <jeremy.kerr@au.ibm.com> Acked-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2014-08-01ATTN: Set up attention area to handle attentionAruna Balakrishnaiah1-0/+5
At present CPU control area ntuple in SPIRA structure is NULL. ATTN component in Service Processor side checks for this field and if its empty, it logs hardcoded SRC (0xBB821410) and generates SYSDUMP. So we have 1 SRC for all failure (assert call) from OPAL side. This makes difficult to debug the issue. Service processor provides attention area interface (FIPS PHyp Attentions spec), so that we can pass SRC and user data (error message) to service processor. This will helps us identify different failures in OPAL. This patch enables attention area and provides interface (update_sp_attn_area()) to add src and user data (error message) through assert macro. Attention SRC format: 1st byte - Opal src type 2-4 bytes - Holds the address of the assert function call Signed-off-by: Aruna Balakrishnaiah <aruna@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-07-02Initial commit of Open Source releaseBenjamin Herrenschmidt1-0/+114
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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