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Adding these properties enables the kernel to function in the same way
that it would if it could no longer access BMC configuration registers
through a backdoor, which may become the default in future.
The comments describe how isolating the host from the BMC could be
achieved in skiboot, assuming all kernels that the system boots
support this. Isolating the BMC and the host from each other is
important if they are owned by different parties; for example, a cloud
provider renting machines "bare metal".
Acked-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Russell Currey <ruscur@russell.cc>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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If the BMC is MBOX protocol aware, request flash reads/writes over the
MBOX regs. This inits the blocklevel for pnor access with mbox-flash.
Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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The mbox registers are accessed via superIO, these need to be
initialised.
The mbox device node won't be present in the device tree hostboot passes
us, so fixup the device tree.
Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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We already support larger parts on the host flash, but the BMC
has always had a 16MB part, so we did not need to enable the 4b
addressing mode.
This enables the 4b addressing mode when the flash is larger than 16MB.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@fr.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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memboot uses bmc system memory instead of a real flash chip. This
patch adds a flash backend for bmc system memory to allow use of the
memboot tool (in external/memboot) to boot the system.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Fixes 64MB chip support, improve Macronix settings, add Micron
chip support, etc...
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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The AMI images use the virtual UART, not the SIO UART, so configuring
the SIO the way we do is incorrect. Additionally, they don't configure
the interrupts properly (bad polarity for VUART and bad number for iBT).
This reworks the inits to fix that up:
- All SIO interrupts are set to level low
- Check if VUART is enabled. If yes, configure and use it (and disable
SIO UART which hostboot might have left enabled).
- Else, reconfigure VUART LPC address and IRQ properly
- Configure iBT LPC address and IRQ properly
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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