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2021-08-06xive/p10: Activate split mode for PHB ESBs when PQ_disable is availableCédric Le Goater1-0/+25
1/3rd of the cache is reserved for PHB ESBs and the rest to IPIs. This is sufficient to keep all the PHB ESBs in cache and avoid ESB cache misses during IO interrupt processing. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Introduce a new OPAL_XIVE_IRQ_STORE_EOI2 flagCédric Le Goater1-1/+1
StoreEOI (the capability to EOI with a store) requires load-after-store ordering in some cases to be reliable. P10 introduced a new offset for load operations to enforce correct ordering and the XIVE driver has the required support since kernel 5.8, commit b1f9be9392f0. OPAL on P10 will advertise support of StoreEOI with a new flag. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Add automatic Context Save and Restore supportCédric Le Goater1-0/+48
The save-restore feature is forced when available. It would have been better to introduce some negotiation but the CAM line value is returned by get_vp_info() before the save-restore feature can be enabled by KVM in xive_native_enable_vp(). This is compatible with the current KVM implementation for P9. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Configure XIVE for fused coresCédric Le Goater1-1/+16
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hw/psi-p10: Configure interrupt offset before notify addrOliver O'Halloran1-10/+10
When configuring the XIVE notification address any currently pending interrupts will be delivered once the the valid bit in the BAR is set. Currently we enable the notify BAR before we've configured the global interrupt number offset for the PSI interrupts. If any PSI interrupt is we'll send an interrupt trigger notification to the XIVE with the wrong interrupt vector (0..15). This can potentially cause a checkstop since there may not be an EAS / IVT configure for that vector. Fix this by registering and masking all the PSI interrupts after we've configured the ESB BAR, but before configuring the notification address and offset. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Introduce new capability bitsCédric Le Goater2-9/+51
These bits control the availability of interrupt features : StoreEOI, PHB PQ_disable, PHB Address-Based Trigger and the overall XIVE exploitation mode. These bits can be set at early boot time of the system to activate/deactivate a feature for testing purposes. The default value should be '1'. The 'XIVE exploitation mode' bit is a software bit that skiboot could use to disable the XIVE OS interface and propose a P8 style XICS interface instead. There are no plans for that for the moment. The 'PHB PQ_disable', 'PHB Address-Based Trigger' bits are only used by the PHB5 driver and we deduce their availability from the capabilities of the first XIVE chip. If called from a PHB4 driver, the capabilities should be set to false. Signed-off-by: Cédric Le Goater <clg@kaod.org> [FB: port to phb4.c] Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06psi/p10: Mask all sources at initCédric Le Goater1-0/+7
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06psi/p10: Introduce xive2_source_mask()Cédric Le Goater2-1/+17
Commit fa161cd89fbf ("hw/psi-p9: Mask OPAL-owned LSIs without handlers") introduced xive_source_mask(). Do the same for P10. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hw/phb5: Add support for 'Address-Based Interrupt Trigger' modeCédric Le Goater2-12/+57
The PHB5 introduces a new Address-Based Interrupt mode which extends the notification offloading to the ESB pages. When ABT is activated, the PHB maps the interrupt source number into the interrupt command address. The PHB triggers the interrupt using directly the IC ESB page of the interrupt number and does not use the notify page of the IC anymore. The PHB interrrupt configuration under ABT is a little different. The 'Interrupt Notify Base Address' register points to the base address of the IC ESB pages and not to the notify page of the IC anymore as on P9. The 'Interrupt Notify Base Index' register is unused. This should improve overall performance. The P10 IC can handle higher interrupt rates compared to P9 and the PHB latency should be improved under ABT. Debug is easier as the interrupt number is now exposed on the PowerBUS. Signed-off-by: Cédric Le Goater <clg@kaod.org> [FB: port to phb4.c] Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hw/phb5: Add support for PQ offloadingCédric Le Goater2-10/+77
The POWER9 DD2.0 introduced a StoreEOI operation which had benefits over the LoadEOI operation : less latency and improved performance for interrupt handling. Because of load vs. store ordering issues in some cases, it had to be deactivates. The POWER10 processor has a set of new features in the XIVE2 and the PHB5 controllers to address this problem. At the interrupt controller level, XIVE2 adds a new load offset to the ESB page which offers the capability to order loads after stores. It should be enforced by the OS when doing loads if StoreEOI is to be used. But this is not enough. The firmware should also carefully configure the PHB interrupt sources to make sure that operations on the PQ state bits of a source are routed to a single logic unit : the XIVE2 IC. The PHB5 introduces a new configuration PQ disable (bit 9) bit for this purpose. It disables the check of the PQ state bits when processing new MSI interrupts. When set, the PHB ignores its local PQ state bits and forwards unconditionally any MSI trigger to the XIVE2 interrupt controller. The XIVE2 IC knows from the trigger message that the PQ bits have not been checked and performs the check using the local PQ bits. This configuration bit only applies to MSIs and LSIs are still checked on the PHB to handle the assertion level. This requires a new XIVE interface to register a HW interrupt source using the IC ESB pages of the allocated HW interrupt numbers, and not the ESB pages of the HW source. This is what this change proposes for MSIs, LSI still being handled the old way. PQ disable is a requirement for StoreEOI. Signed-off-by: Cédric Le Goater <clg@kaod.org> [FB: port to phb4.c] Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Add option flags to the XIVE exploitation modeCédric Le Goater1-7/+22
Change sligthly the semantic of the parameter of the opal_xive_reset() OPAL call to configure the interrupt mode of the machine and, at the same time, to configure the associated options. These options only apply to the XIVE exploitation mode. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hw/phb5: Add initial supportJordan Niethe3-76/+183
The PHB5 logic on P10 is pretty close to the P9's version. So we keep our base phb4 implementation and just add the few changes within if statements. Signed-off-by: Jordan Niethe <jpn@ozlabs.au.ibm.com> [clg: misc cleanups and fixes ] Signed-off-by: Cédric Le Goater <clg@kaod.org> [Fixed compilation issue - Vasant] Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [Nick: Unify PHB4/PHB5 drivers ] Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [Mikey: set default lane eq settings for phb5] Signed-off-by: Michael Neuling <mikey@neuling.org> [FB: squash commits + small cleanup ] Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06psi/p10: Activate StoreEOICédric Le Goater1-1/+14
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06psi/p10: Activate 64K ESB pagesCédric Le Goater1-3/+4
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Add a XIVE2 driverCédric Le Goater5-9/+4479
The XIVE2 interrupt controller of the POWER10 processor follows the same logic than on POWER9 but the HW interface has been largely reviewed. It has a new register interface, different BARs, extra VSDs, new layout for the XIVE structures, and a set of new features which are described below. The OPAL XIVE2 driver code activating this controller was duplicated from P9 for clarity as the registers and structures have changed considerably. The same OPAL interface is implemented for OS compatibility and it should not impact existing Linux kernels, KVM included. Guest OS is not impacted either. Support for new features will be implemented in time and will require new support from the OS. * XIVE2 BARS The interrupt controller BARs have a different layout outlined below. Each sub-engine has now own its range and the indirect TIMA access was replaced with a set of pages, one per CPU, under the IC BAR: - IC BAR (Interrupt Controller) . 4 pages, one per sub-engine . 128 indirect TIMA pages - TM BAR (Thread Interrupt Management Area) . 4 pages - ESB BAR (ESB pages for IPIs) . up to 1TB - END BAR (ESB pages for ENDs) . up to 2TB - NVC BAR (Notification Virtual Crowd) . up to 128 - NVPG BAR (Notification Virtual Process and Group) . up to 1TB - Direct mapped Thread Context Area (reads & writes) OPAL does not use the grouping and crowd capability. * Virtual Structure Tables XIVE2 adds new tables types and also changes the field layout of the END and NVP Virtualization Structure Descriptors. - EAS - END new layout - NVT was splitted in : . NVP (Processor), 32B . NVG (Group), 32B . NVC (Crowd == P9 block group) 32B - IC for remote configuration - SYNC for cache injection - ERQ for event input queue The setup is slighly different on XIVE2 because the indexing has changed for some of the tables, block ID or the chip topology ID can be used. * XIVE2 features SCOM and MMIO registers have a new layout and XIVE2 adds a new global capability and configuration registers. The lowlevel hardware offers a set of new features among which : - cache injection mechanism - 4 cache watch engines - a configurable number of priorities : 1 -8 - StoreEOI with load-after-store ordering is activated by default - new sync/kill operations for cache operations Other features will have some impact on the Hypervisor and guest OS when activated, but this is not required for initial support of the controller. - Gen2 TIMA layout - A P9-compat mode, or Gen1, TIMA toggle bit for SW compatibility - Automatic Context save & restore - increase to 24bit for VP number - New escalations schems : ESB, Adaptive, CPPR POWER10 adds support for User interrupts. When configured, the XIVE2 controller can notify directly user processes using the Event Based Branch exception line of the thread. If not running, the OS is notified through an escalation event. New OPAL and PAPR interfaces will be required and OS support needs to be studied. * XIVE2 P9-compat mode, or Gen1 The thread interrupt management area (TIMA) is a set of pages mapped in the Hypervisor and in the guest OS address space giving access to the interrupt thread context registers for interrupt management, ACK, EOI, CPPR, etc. XIVE2 changes slightly the TIMA layout with extra bits for the new features, larger CAM lines and the controller provides configuration switches for backward compatibility. This is called the XIVE2 P9-compat mode, of Gen1 TIMA. It impacts the layout of the TIMA and the availability of the internal features associated with it, Automatic Save & Restore for instance. Using a P9 layout also means setting the controller in such a mode at init time. The XIVE2 driver in OPAL chooses to initialize the XIVE2 controller with a XIVE2/P10 TIMA directly because the layouts are compatible with the Linux PowerNV and the guest OSes expectations. For KVM support, the OPAL calls abstract the HW interface and no assumption is made on the OS CAM line width. * Activating new XIVE2 features Everything related to OPAL internals such as the use of the new cache sync mechanism can be implemented in time without impact on the OS. Other features will require new device tree properties exposed to the OS and extra support for the OS. Automatic Context save & restore is one of the first feature which should be looked at. * XICS-over-XICS driver (P8 compatibility) The P8 emulation mode is an OPAL compat interface used for Linux kernels which did not have XIVE native support. This was useful for POWER9 bringup but it is much less now. As it was adding a lot of complexity and reducing the interrupt controller resources, this mode is not available in the XIVE2 driver for POWER10. It will still be possible to add this compat mode in the future if required. The OS will have to reset the driver at boot time, like on POWER9. * Impact on other drivers (PSI, PHB, NPU) Interrupts are allocated in a very similar way. Each controller might have different ESB characteristics, StoreEOI support, 64K pages for PSI. All is in place to support these changes already. PHB5 will have support for "address-based trigger mode", probably in the DD2.0 time frame when verification is completed. When activated, the XIVE IC ESB pages will be used instead of the PHB ESB pages for a lower interrupt latency. LSI will still use old fashion triggers without StoreEOI. * Yet to be addressed : - OPAL P10 interface incomplete (stop states) - Clarify the PHB5 strategy regarding the use of the XIVE IC ESB pages instead of the PHB ones when address-based trigger mode is supported. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06platform: Add Denali platform supportVasant Hegde1-0/+1
Denali is P10 system. But FSP interaction (MBOX protocol) is same as ZZ. Hence add denali platform detection code inside zz.c for now. We can think of adding separate platform later. Also enable : - P10 TCE mapping support - Detect PHBs Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hw/imc: Power10 supportAnju T Sudhakar2-10/+56
POWER10 IMC support: Add POWER10 scom addresses for IMC Add support for IMC trace-mode Fix the catalog subit for POWER10 Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hw/nx: Enable p10 DARNRyan Grimm1-7/+22
Init and enable NCU DARN BAR on sibling cores as well for fused core mode. Signed-off-by: Ryan Grimm <grimm@linux.ibm.com> Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com> [Folded Vaidy's fused core support fix - Vasant] Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06NX: Set VAS RMA write BAR register on P10Haren Myneni2-0/+54
For each NX instance, VAS RMA write BAR register should be set with the corresponding VAS RMA BAR value. Refer section: 5.30 VAS RMA write BAR (P10 NX work Book V1.01) Signed-off-by: Haren Myneni <haren@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06VAS: Enable VAS on P10Haren Myneni1-5/+24
Enable VAS on P10 based on "ibm,power10-vas-x" compatible string and export the new compatible property to kernel. Also do not set foreign address enable for VAS/NX RMA BAR From section 1.3.3.1 in VAS workbook, RA(0:12) = 0's for VAS/NX RMA BAR. It means foreign address enable bit (RA(11) should be 0 for RMA VAR. But this bit has to be set for paste base address which is used for COPY/PASTE. Signed-off-by: Haren Myneni <haren@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06VAS: Define Remote Memory Access paste address on P10Haren Myneni1-3/+73
Paste base address format is changed on p10. Instead of node/chip IDs, Primary topology index is used to define paste base address. Also RA(11) bit is used to define the foreign address. Changes to define the paste base address for each VAS engine with the new format on P10. Signed-off-by: Haren Myneni <haren@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hw/phys-map/p10: Add P10 MMIO mapAlistair Popple2-4/+101
Adds a phys map for P10 based on the MMIO spreadsheet. Also updates the phys map test to take a parameter which selects which map to test. - Introduce new BAR for the PC subengine of XIVE2 On P10, the NVP (Process) and NVG (Group) pages share the MMIO range. The even page gives access to the NVP structure and the odd page to the NVG structure. OPAL only uses the NVP. - Introduce new BARs for the VC subengine of XIVE2 On P10, the source ESB pages and END ESB pages have now their own MMIO range. - Increase the MMIO range for the END ESB pages The range was increased to 2TB to be able to address more END entries. We now have a maximum of 16M entries per chip. The END and ESB ranges are reordered for alignment. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> [Folded Cedric's patches - Vasant] Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06prd: Add base P10 supportOliver O'Halloran1-0/+5
Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06phys/P10: Use topology index to get phys mappingVasant Hegde2-3/+22
This fixes multipchip rainier boot issue. for Rainer: chip0: ibm,primary-topology-index = < 0x0>; chip1: ibm,primary-topology-index = < 0x4>; chip2: ibm,primary-topology-index = < 0x8>; chip3: ibm,primary-topology-index = < 0xc>; for Denali: node0: chip0: ibm,primary-topology-index = < 0x0>; chip1: ibm,primary-topology-index = < 0x1>; chip2: ibm,primary-topology-index = < 0x2>; chip3: ibm,primary-topology-index = < 0x3>; node1: chip0: ibm,primary-topology-index = < 0x4>; chip1: ibm,primary-topology-index = < 0x5>; chip2: ibm,primary-topology-index = < 0x6>; chip3: ibm,primary-topology-index = < 0x7>; Note that bmc_create_node() gets called very early in the boot process. Hence we have to traverse through HDAT ntuple to get right topology index. May be we can optimize pcid_to_topology_idx() function as its pretty much duplicate of pcid_to_chip_id(). But for now lets keep it as separate function. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Ryan Grimm <grimm@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06occ: Add POWER10 supportVaidyanathan Srinivasan3-14/+165
Add support for parsing OCC on Power10 to populate the pstate information. Also enables OCC on P10 Denali system. Co-authored-by: Pratik R. Sampat <psampat@linux.ibm.com> Co-authored-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com> Signed-off-by: Pratik R. Sampat <psampat@linux.ibm.com> Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06psi/p10: Activate P10 interruptsCédric Le Goater1-1/+63
Behave as P9 for now until we know more on P10. Interface should be the same, apart from the size of the ESB pages. Signed-off-by: Cédric Le Goater <clg@kaod.org> [Fixed suprious interrupt issue - Vasant] Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06Basic P10 stop state supportVaidyanathan Srinivasan2-16/+126
Adds support for STOP0 lite, STOP2 and STOP3 for Power10 with the following latencies, residency requirements: latency residency stop0lite 1us 10us stop0 10us 100us stop2 20us 200us stop3 45us 450us Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com> Signed-off-by: Pratik R. Sampat <psampat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hw/chiptod: Add POWER10 supportNicholas Piggin1-15/+59
POWER10 changes to use the SCOM addressing mode, as it was found to be more robust than the core ID addressing mode. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hw/p8-i2c: Add POWER10 supportOliver O'Halloran1-15/+14
Early P8s didn't have the I2C interrupt, but all the subsequent chips have one. Flip the interrupt support checking so the old chips are the special case rather than having to add a new entry for every new chip. P10 added several additional flag registers and moved the existing flag register. The actual data bits have not changed so the existing handshake protocol between the OCC and OPAL works just fine. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06Initial POWER10 enablementNicholas Piggin4-11/+58
Co-authored-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Co-authored-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com> Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com> Co-authored-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Co-authored-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Co-authored-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Co-authored-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-04POWER9 Cleanups: Don't force clear SPW bitsPratik R. Sampat1-9/+5
SLW force-cleared Special wakeup bits that could hold power management. However, SLW should expect these bits to be cleared at this point, hence only read and the report on the SPW bits to find anomalies instead. Signed-off-by: Pratik R. Sampat <psampat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-07-19powercap: occ: Set occ_set_powercap as const attributePratik R. Sampat1-1/+1
The commit fixes the compile time warning suggestion of setting occ_set_powercap as a candiate for the attribute 'const'. Fixes: c6aabe3f2eb5 (powercap: occ: Add a generic powercap framework) Signed-off-by: Pratik R. Sampat <psampat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-07-19hw/imc: Refactor trace-imc macrosMadhavan Srinivasan1-11/+19
Also setup_imc_scoms() moves early in imc_init() to avoid any access of platform specific values before initialization. Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-06-30hw/imc: Do scoms on the secondary core in fused core mode for core-imc countersAnju T Sudhakar1-63/+90
Core IMC hardware mandates initiating of three scoms to enable or disable of the Core IMC engine. This has to be done for each core, and is done in the opal_imc_counters_init(). In fused core mode, the scom has to be done explicitly for the secondary core to enable or disable core IMC engine in that core. Do the scom for the secondary core, by calculating the core id from the incoming cpu id. This patch is based on the series, Initial fused-core support for POWER9 [v5]: https://lists.ozlabs.org/pipermail/skiboot/2020-April/016778.html Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-06-30hw/imc: Use the xscom macros for IMC based on platformAnju T Sudhakar1-34/+61
The xscom macros defined in the skiboot are platform specific. IMC opal APIs use these xscom definitions, to read and write to scom ports. Cleanup the code to pick the appropriate xscom macro definition based on the running platform. Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-06-30hw/imc: Cleanup code to define scom addr for IMC at run timeAnju T Sudhakar1-2/+32
Currently scom addresses for IMC are defined at compile time. The scom addresses may vary for different processor generations. So clean up the code to pick the right scom addresses, based on the processor version at run time. Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-06-30hw/p8-i2c: Make OCCFLG register base address configurable at runtimeOliver O'Halloran1-9/+15
Prepare for POWER10 support which changes the OCCFLG register base address. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> [Replaced perror with prlog - Vasant] Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-06-30hw/p8-i2c: Add buses at runtimeOliver O'Halloran1-8/+75
When booting skiboot we initialise any I2C masters after probing the platform, but before initialising the platform (or NVRAM). Due to this we need to ensure that all the I2C masters we might want to use are in the DT before the platform is initialised. This causes problems since we might want to add another master (e.g. on witherspoon we might need to add a port for the I2C OpenCAPI I2C bus). It's possible to hack around this by adding a new node in the probe function, but the probe function runs very early before many essential services are initialised (e.g. LPC). We might want to add another I2C bus after learning that we have a riser card installed and it's not possible to do that until later in boot. To accommodate those use cases we can add support for adding a new bus at runtime. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-06-30hw/p8-i2c: Move port init into a separate functionOliver O'Halloran1-48/+45
Move it out in preparation for adding the ability to add new ports on the fly. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-06-30hw/p8-i2c: Set poll interval from the current portOliver O'Halloran1-16/+7
The rate at which we need to poll the master depends on the speed of the bus. Faster I2C buses will require more frequent polling so it doesn't make a whole lot of sense to set this on a per-master basis. This patch sets the master's polling interval to a per-port setting calculated from the port speed. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-06-30hw/p8-i2c: Print interrupt status per masterOliver O'Halloran1-11/+5
Whether I2C interrupts work or not depends on the type of master. Currently we print a single message to indicate whether IRQs work or not, but this will be wrong if we have I2C interrupts on the host and we happen to probe a Centaur I2C master first. Fix this by adding a message to the per-master print indicating whether the master has an interrupt or not. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-06-30hw/p8-i2c: Add p8_i2c_find_bus_by_port()Oliver O'Halloran1-0/+26
Adds a way to find the struct i2c_bus for a given chip ID, engine ID, and port ID. HDAT indicates which I2C master is relevant using this information so it comes up a fair bit. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-06-30VAS: Define p9_get_rma_bar()Haren Myneni1-54/+65
Setting the Remote Memory Access BAR address is used in a couple of places which should be defined as a common function. On p10, paste base address format is changed (using primary topology index instead of node/chip IDs). This patch adds p9_get_rma_bar() for P9. Whereas get_rma_bar() on P10 and future processors which will be added in later patches. Signed-off-by: Haren Myneni <haren@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-05-28uart: Give SIMICS some more timeCédric Le Goater1-0/+3
Increase timeout introduced in commit 6bf21350da32 ("uart: Drop console write data if BMC becomes unresponsive") when running under SIMICS. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-05-13hw/imc: Disable only nest_imc devices if pause_microcode() failsMadhavan Srinivasan1-2/+16
During opal boot, in imc_init(), 24x7/IMC microcode state is checked and if it is not in running or pause state, currently all the imc devices are removed from device tree. Instead, remove only the nest imc devices. Core/Thread/Trace imc devices are not related to 24x7 microcode. Patch adds a function to remove specific imc device type and the same is used, when pause_microcode() fails, to remove nest imc device types from the device tree. Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-04-07hw/ipmi: Fix misleading-indentation failuresVasant Hegde1-1/+1
Hitting below issue on recent distro (fedora-rawhide). sample failure: --------------- [ HOSTCC ] hw/ipmi/test/run-fru.c In file included from hw/ipmi/test/run-fru.c:10: hw/ipmi/test/../ipmi-fru.c: In function 'fru_fill_product_info': hw/ipmi/test/../ipmi-fru.c:80:17: error: this 'if' clause does not guard... [-Werror=misleading-indentation] 80 | if (rc < 1) return OPAL_PARAMETER; rc; }) | ^~ hw/ipmi/test/../ipmi-fru.c:102:18: note: in expansion of macro 'FRU_INSERT_STRING' 102 | index += FRU_INSERT_STRING(&buf[index], info->manufacturer); | ^~~~~~~~~~~~~~~~~ hw/ipmi/test/../ipmi-fru.c:80:52: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the 'if' 80 | if (rc < 1) return OPAL_PARAMETER; rc; }) | ^~ hw/ipmi/test/../ipmi-fru.c:102:18: note: in expansion of macro 'FRU_INSERT_STRING' 102 | index += FRU_INSERT_STRING(&buf[index], info->manufacturer); | ^~~~~~~~~~~~~~~~~ Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Reviewed-by: Dan Horák <dan@danny.cz>
2021-03-31phb4: Avoid MMIO load freeze escalation on every chipMahesh Salgaonkar1-1/+5
The commit f397cc30bdf8 ("phb4: Only escalate freezes on MMIO load where necessary") introduced a change to restrict escalation to the chips that actually need it. However it missed one case which still causes the escalation on every chip. This affects EEH recovery to cause full PHB reset on some chips which is not necessary. This patch fixes that. Also, add a check for p9 chip in phb4_escalation_required() function. Cc: skiboot-stable@lists.ozlabs.org Signed-off-by: Mahesh Salgaonkar <mahesh@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-02-12phb4/5: Fix printing of device secondary status register.Mahesh Salgaonkar1-1/+1
The commit e73cf72d1f97 ("phb4: make endian-clean") accidently missed printing correct value for PCI device secondary status register. [ 1654.399387394,3] PHB#0033[3:3]: devCmdStatus = 00100107 [ 1654.399389575,3] PHB#0033[3:3]: devSecStatus = 00100107 after this patch: [ 1620.415289504,3] PHB#0033[3:3]: devCmdStatus = 00100107 [ 1620.415291622,3] PHB#0033[3:3]: devSecStatus = 00002000 Fixes: e73cf72d ("phb4: make endian-clean") Signed-off-by: Mahesh Salgaonkar <mahesh@linux.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-02-04phb4: Disable TCE cache line bufferFrederic Barrat1-0/+1
This patch implements a circumvention for HW557787. It disables the TCE cache line buffer as, under heavy loads, there's a possibility of an entry being re-allocated incorrectly. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-02-04hw/phb4: Use inclusive language, replace the word 'whitelist'Philippe Mathieu-Daudé1-10/+10
Follow the inclusive terminology from the "Conscious Language in your Open Source Projects" guidelines [*] and replace the word "whitelist" appropriately. [*] https://github.com/conscious-lang/conscious-lang-docs/blob/main/faq.md Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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