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2021-12-23chiptod: properly zero TB SPR when cleaning up for invalid TBNicholas Piggin1-1/+2
The existing sequence writes TBU twice and leaves TBL unchanged. This may not really matter if it's being resynced from the chiptod soon, but it's possible it could clear a parity error. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-09hw/lpc: fix compilation errorNicholas Piggin1-0/+1
Compilation can fail when building tests if the opal-api.h include is not pulled in via headers. Include it directly. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-09ccan: switch list_add_before/after arguments to match upstreamNicholas Piggin1-1/+1
Upstream ccan uses (list, existing entry, new entry) parameter ordering rather than (list, new entry, existing entry) ordering. Switch these to make syncing with upstream simpler. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-21xive/p10:: Declare xive2 DT node as an interrupt-controllerFrederic Barrat1-1/+6
This patch fixes errors seen when linux looks for the interrupt to use for a device LSI: pci X:Y:Z of_irq_parse_pci: failed with rc=-22 The of/irq parsing code requires those new properties to be able to map the interrupt specifier correctly. It was not needed before comitting cd12ea6d8e1 ("interrupts: Do not advertise XICS support on P10"), because the LSI mapping code was defaulting to the XICS interrupt controller node, which is now removed (and had those properties). Fixes: cd12ea6d8e1 ("interrupts: Do not advertise XICS support on P10") Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: Add support for OpenCAPI Persistent Memory devices.Christophe Lombard4-16/+137
Lowest Point of Coherency (LPC) memory allows the host to access memory on an OpenCAPI device. When the P10 chip accesses memory addresses on the AFU, the Real Address on the PowerBus must hit a BAR in the PAU such as GPU-Memory BAR. The BAR defines the range of Real Addresses that represent AFU memory. The two existing OPAL calls, OPAL_NPU_MEM_ALLOC and OPAL_NPU_MEM_RELEASE are used to manage the AFU momory. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: mmio invalidatesChristophe Lombard2-0/+39
The remaining translation mode: OpenCAPI 5.0 with TLBI/SLBI Snooping, is not used due to performance problems caused by the mismatch between the ERAT and Bloom Filter sizes. When the Address Translation Mode requires TLB and SLB Invalidate operations to be initiated using MMIO registers, a set of registers like the following is used: • XTS MMIO ATSD0 LPARID register • XTS MMIO ATSD0 AVA register • XTS MMIO ATSD0 launch register, write access initiates a shoot down • XTS MMIO ATSD0 status register Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: update current opal call functionsChristophe Lombard2-0/+165
Update the content of three current OPAL API calls to support PAU. - OPAL_NPU_SPA_SETUP The Shared Process Area (SPA) is a table containing one entry (a "Process Element") per memory context which can be accessed by the OpenCAPI device. - OPAL_NPU_SPA_CLEAR_CACHE The PAU keeps a cache of recently accessed memory contexts. When a Process Element is removed from the SPA, the cache for the link must be cleared. - OPAL_NPU_TL_SET The Transaction Layer specification defines several templates for messages to be exchanged on the link. During link setup, the host and device must negotiate what templates are supported on both sides and at what rates those messages can be sent. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: link trainingChristophe Lombard1-0/+529
Add elementary functions to handle a phb complete, fundamental and hot resets. For the time being, specific creset and hreset are not supported. A complete fundamental reset is based on the following steps, in this order: - Place all bricks into Fence state - Disable BARs - Reset ODL to Power-on Values - Set the i2c reset pin in output mode - Initialize PHY Lanes - Deassert ODL reset - Clear the the i2c reset pin - Unfence bricks - Enable BARs - Enable ODL training mode Link training is also set up. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: phy initChristophe Lombard2-1/+311
Follow the Procedure IO_INIT_RESET_PON as described in the P10 OPHY workbook document to reset and initialize the PHY lanes. The memory mapped SRAM (64 bit aligned) has to be used to configure the PHY, which is reachable the linked registers: address and data. The different links can be configured at the same time, that implies using a global lock to avoid conflicts. Authored-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: hmi scom dumpChristophe Lombard2-24/+47
This patch add a new function to dump PAU registers when a HMI has been raised and an OpenCAPI link has been hit by an error. For each register, the scom address and the register value are printed. The hmi.c has been redesigned in order to support the new PHB/PCIEX type (PAU OpenCapi). Now, the *npu* functions support NPU and PAU units of P8, P9 and P10 chips. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: complete phb opsChristophe Lombard1-0/+137
Add more PHB interfaces: - to control pci error type in case of freeze. - add the addresses of the registers needed by the OS to handle translation failures. - to detect the fence state of a specific brick - to configure BDF (Bus Device Function) and PE (Partitionable Endpoint) for context identification. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: enable interrupt on errorChristophe Lombard1-0/+157
The default action for the errors (unexpected errors on the opencapi link) reported in the PAU FIR2 registe is mostly set to system checkstop. This patch changes the default action of those errors so that the PAU will raise an interrupt instead. Interrupt information are logged so that the error can be debugged and linux can catch the event. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: translation layer configurationChristophe Lombard1-0/+192
Next main part of the hypervisor PAU initialization. The P10 PAU supports two OpenCAPI links. The PAU provides various configuration selections for both of the OCAPI Link Transaction Layer functions (OTLs). These include a link enable, behavior controls, debug modes, and virtual channel credits to send to the AFU. The OTL Configuration 0, OTL Configuration 1, OTL Configuration 2, and TLX Credit Configuration registers are used to control these functions. This patch completes the PAU configuration following the sections 17.1.3.4 to 17.1.3.10.2 of the workbook document. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: enabling opencapiChristophe Lombard1-0/+222
Enable OpenCAPI mode for each brick which are connected to be used in this mode. This is be done through 7 steps as described in the P10 OCAPI 5.0 Processing Unit Workbook document, section: 17.1.3.1 Enabling OpenCAPI. The following sequences must be performed: 1. Set Transport MUX controls to select OpenCAPI 2. Enable Clocks in XSL 3. Enable Clocks in MISC 4. Set NPCQ configuration 5. Enable XSL-XTS Interfaces 6. Enable State-machine allocation Enabling the NTL/GENID BARS allows to access to the MMIO registers. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: create phbChristophe Lombard1-1/+233
Implement the necessary operations for the OpenCAPI PHB type and inform the device-tree properties associated. The OpenCapi PCI config Addr/Data registers are reachable through the Generation-ID Registers MMIO BARS. The Config Address and Data registers are located at the following offsets from the AFU Config BAR plus 320 KB. • Config Address for Brick 0 – Offset 0 • Config Data for Brick 0 – Offsets: ◦ 128 – 4-byte config register • Config Address for Brick 1 – Offset 256 • Config Data for Brick 1 – Offsets: ◦ 384 – 4-byte config register Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: assign barsChristophe Lombard2-8/+126
Configure early PAU Global MMIO BAR registers to allow PAU MMIO register accesses. This is done for each PAU. Enable the Powerbus interface is mandatory for MMIO accesses. For each OpenCAPI device, configure the bar registers to access to the AFU MMIO and to the AFU Config Addr/Data registers. AFU Config/Data registers = GENID_ADDR (from phy_map file) + 320K (= 0x50000) Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: introduce supportChristophe Lombard2-1/+225
OpenCapi for P10 is included in the P10 chip. This requires OCAPI capable PHYs, Datalink Layer Logic and Transaction Layer Logic to be included. The PHYs are the physical connection to the OCAPI interconnect. The Datalink Layer provides link training. The Transaction Layer executes the cache coherent and data movement commands on the P10 chip. The PAU provides the Transaction Layer functionality for the OCAPI link(s) on the P10 chip. The P10 PAU supports two OCAPI links. Six accelerator units PAUs are instantiated on the P10 chip for a total of twelve OCAPI links. This patch adds PAU opencapi structure for supporting OpenCapi5. hw/pau.c file contains main of PAU management functions. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19npu2: move opal apiChristophe Lombard2-35/+69
Move the OPAL entry points for npu2 opencapi to the common opal NPU file. This prepares us to add same entries for PAU opencapi in this common file. No functional change. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19AWAN simulator support for P10Ryan Grimm1-2/+5
This patch enables Skiboot to initialize and Linux to boot to user space on the AWAN core and chip models. We need the distinction between core and chip models because the core models do not have an XSCOM unit, CHIPTOD, nor RNG. The chip model does have them and they work. So, add a device_type property to the awan node to distinguish core from chip. Sample DTS are provided for the core and chip models in external/awan. Just like Mambo, we need to return in slw_init before trying to initialize SLW. Without an XSCOM unit in the device tree for the core model, the SLW code path eventually fails an assert due to lack of chips. This commit defines a QUIRK_AWAN where previously Mambo used QUIRK_MAMBO_CALLOUTS so now Mambo and AWAN core both work. Also, fix up chip quirks so the core model and chip model boot and initialize the appropriate units. Disable sreset and power management in a couple spots because the chip model does not support stop with EC=1 and enter_p9_pm_state spins in the branch-to-self after stop. Provide an external/awan/README.md with a high-level view of booting in the environment. Signed-off-by: Ryan Grimm <grimm@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19flash: AST BMC endian fixesNicholas Piggin1-3/+11
Fix endian for the 4-byte LPC copy similarly to other flash drivers. This allows flash to be detected on POWER8 AST BMC systems with a LE skiboot. Fix incorrect comments in those other drivers while we're here. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19phb3: make endian-cleanNicholas Piggin1-158/+159
Convert phb3 dt construction and in-memory hardware tables to use explicit endian conversions. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19Remove support for POWER8 DD1Nicholas Piggin2-379/+12
This significantly simplifies the SLW code. HILE is now always supported. Reviewed-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19phb4: annotate tbl_pest with endian typesNicholas Piggin1-12/+7
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19interrupts: add_opal_interrupts avoid NULL dereference on P10 mamboNicholas Piggin1-0/+3
On P10, get_ics_phandle() calls xive2_get_phandle() directly. This results in a NULL dereference on mambo when xive2 is not set up. This was caught with the virtual memory boot patch on P10 mambo. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-02phb5: Remove obsolete capp-related propertiesFrederic Barrat1-7/+10
This patch removes the following properties from PHB entries in the device tree on P10, since there's no CAPP any more and the properties no longer make sense: ibm,phb-indications ibm,capp-timebase-sync ibm,capi-flags It has no effect on linux: some were already ignored and others won't even be read since the cxl driver (the only consumer) already fails early on P10. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-02external/mambo: Updates for POWER10 configuration for DD2.0Nicholas Piggin1-1/+1
Update PVR and mambo f000f bits: - Set POWER10 to DD2.0 Update SIM_CTRL and SIM_CTRL1 bits: - Set the LPAR-per-core mode bit. This is required for SMT KVM to work. - Set ARC0/ARC1 bits which enable atomic RC update interrupts (not hardware updates), which matches implementation. - Enable DEXCR, HAIL, ROP, BHRB disable, block BHRB writes in PR=0, and RFC02628 on POWER10. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-09-09npu3: Remove GPU support on SwiftFrederic Barrat5-3186/+3
npu3 was only used on the Swift platform to add support for GPUs (nvlink). The Swift platform has never left the lab and support for GPUs on it is pretty much dead. So let's remove it. The patch removes all related code. Device tree entries are no longer created and in the very unlikely case that someone is still trying to boot it, the linux nvlink discovery code should be quiet. Tested by booting on Swift with no GPU. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-27phb4/5: Escalate page-level TCE killsFrederic Barrat1-0/+8
An hw issue was found on P10 (HW560152) where a page-level TCE kill can be dropped if there are enough TCE kill requests already being processed. The net effect is that data integrity is not guaranteed. The circumvention is to stay away from page-level kills and escalate those to PE kills. Which hurts performance. It also affects P9. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-18interrupts: Do not advertise XICS support on P10Cédric Le Goater1-0/+5
We only support the XIVE interface. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-18xive/p10: Fix mismatch errors when DEBUG=1Cédric Le Goater1-0/+3
HW has some reserved fields which break the comparison when checking END cache updates. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-18xive/p10: Fix xive_special_cache_check when DEBUG=1Cédric Le Goater1-1/+1
The special cache check done when skiboot is compiled with DEBUG is incompatible with Automatic Context Save and Restore. Random data is written in the NVP to check that cache updates are correct but this can lead to a checkstop raised by the XIVE interrupt controller. When the NVP Valid (0) bit, the hardware controlled H (7) bit, and the Checked Out bit (45) are all ones at the same time, the HW thinks that the NVP entry is checked out by a thread and does not allow the cache write to occur. Make sure that the valid bit is not set on the NVP. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hw/chiptod: Abort if core frequency is not setVasant Hegde1-0/+6
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hw/chiptod: Retry the sync procedure on failureRyan Grimm1-10/+23
The chiptod sync will sometimes fail and then sync successfully after a retry. So, try an arbitrary 10 numbers of times before we either abort() on main procedure fail or disable threads on secondary procedure fail. Also, put a message on the log if secondaries fail so we have evidence in the log when they aren't enabled. Signed-off-by: Ryan Grimm <grimm@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive2: Add NCU_SPEC_BAR to stop engine for restoreVaidyanathan Srinivasan1-3/+24
P10 Stop engines have apis similar to P9 to set xscom restores after wakeup from deep-sleep states. This xscom restore will be used to support STOP11 on P10. Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com> Signed-off-by: Pratik Rajesh Sampat <psampat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06libpore: P10 stop-api supportPratik Rajesh Sampat1-4/+82
Update libpore with P10 STOP API. Add minor changes to make P9 stop-api and P10 stop-api to co-exist in OPAL. These calls are required for STOP11 support on P10. STIOP0,2,3 on P10 does not lose full core state or scoms. stop-api based restore of SPRs or xscoms required only for STOP11 on P10. STOP11 on P10 will be a limited lab test/stress feature and not a product feature. (Same case as P9) Co-authored-by: Pratik Rajesh Sampat <psampat@linux.ibm.com> Signed-off-by: Pratik Rajesh Sampat <psampat@linux.ibm.com> Co-authored-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com> Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com> Co-authored-by: Ryan Grimm <grimm@linux.ibm.com> Signed-off-by: Ryan Grimm <grimm@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06phb5: Fix PHB max link speed definition on P10Frederic Barrat1-2/+2
Not all PHBs are capable of GEN5 speed on P10. In all PEC configurations, the first PHB is the only one which can handle GEN5. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06phb4/5: Fix PHB link width detection to avoid useless retrainingsFrederic Barrat1-11/+80
On P9 and P10, the PCI express controller (PEC) controls a set of 16 lanes, which can be grouped to form link(s) of various width (4, 8 or 16 lanes). A PCI host bridge (PHB) is handling each link. How many PHBs are active in each PEC is configurable per chip and vary between 2 chips in a system. Therefore PHBs have different link width. The link width of the PHB is used to check if the link is trained optimally and can cause link training retries if that's not the case. We were reading the max link width of a PHB from the link capability register of the PCI express capability of the root bridge. But that value is always an overshoot as it needs to accommodate any PEC configuration. It was hard to fault on P9, as a PEC needs to be trifurcated to start noticing a difference and the device-supported width can also mask it. But on P10, it's also noticeable on bifurcated configuration so it's a bit easier to spot. For example, on P10, PHB0 reports a supported width of 16 in its link capability register because that's what is needed in case of no furcation, but if the PEC is bifurcated or trifurcated, only 8 lanes are wired. So we won't be able to train at more than x8. If we believe the PHB is x16-capable, then we'll retrain the link, potentially several times, thinking it's not optimal, which is a waste of time. This patch finds out the real maximum link width of each PHB, which may require to go check the PEC configuration. The logic is the same on P9 and P10 though the hardware implementations differ slightly. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06phb4: Cleanup PEC config discovery in CAPI modeFrederic Barrat1-8/+9
Small cleanup when reading the PEC config when setting up CAPI, in preparation for P10. Scom addresses vary between P9 and P10 and we'll be accessing more than one PCI chiplet. No functional change. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06phb5: Workaround for PCI bug HW551382Frederic Barrat1-0/+35
The workaround forces a state machine deep in the PHB to start from scratch and to block its evolution until after the link has been reset. It applies on all paths where the link can go down unexpectedly, though it's probably useless on the creset path, since we're going to deep-reset the PHB anyway. But it doesn't hurt and it keeps the set/unset path symmetrical. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06phb5: Enable Gen5Michael Neuling1-4/+8
Registers for Gen5 have been initialized in a previous patch. So let's activate it! Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06phb5: Add register inits specific to Gen5Frederic Barrat1-5/+13
Update init sequence to take into account Gen5. Define default equlization settings if HDAT is not used. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06phb5: Activate StoreEOI for LSIsCédric Le Goater1-1/+1
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Change alignment of the queue overflow pagesCédric Le Goater1-2/+18
The Memory Coherence Directory uses 16M "granule" to track shared copies of a cache line. If any cache line within the 16M range gets touched by someone outside of the group, the MCD forces accesses to any cache line within the range to include everyone that might have a shared copy. Allocate the queue overflow pages and use a 16M alignment to avoid sharing with other structures and reduce traffic on the PowerBus. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Tune max_entries_in_modified when split_mode is onCédric Le Goater1-0/+1
This reduces the number of entries currently modified in the ESB cache. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Activate has_array when PQ_disable is availableCédric Le Goater1-3/+8
hash_array is an Internal cache hashing optimization. It tracks for ESBs where the original trigger came from so that we avoid getting the EAS into the cache twice. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Activate split mode for PHB ESBs when PQ_disable is availableCédric Le Goater1-0/+25
1/3rd of the cache is reserved for PHB ESBs and the rest to IPIs. This is sufficient to keep all the PHB ESBs in cache and avoid ESB cache misses during IO interrupt processing. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Introduce a new OPAL_XIVE_IRQ_STORE_EOI2 flagCédric Le Goater1-1/+1
StoreEOI (the capability to EOI with a store) requires load-after-store ordering in some cases to be reliable. P10 introduced a new offset for load operations to enforce correct ordering and the XIVE driver has the required support since kernel 5.8, commit b1f9be9392f0. OPAL on P10 will advertise support of StoreEOI with a new flag. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Add automatic Context Save and Restore supportCédric Le Goater1-0/+48
The save-restore feature is forced when available. It would have been better to introduce some negotiation but the CAM line value is returned by get_vp_info() before the save-restore feature can be enabled by KVM in xive_native_enable_vp(). This is compatible with the current KVM implementation for P9. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06xive/p10: Configure XIVE for fused coresCédric Le Goater1-1/+16
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hw/psi-p10: Configure interrupt offset before notify addrOliver O'Halloran1-10/+10
When configuring the XIVE notification address any currently pending interrupts will be delivered once the the valid bit in the BAR is set. Currently we enable the notify BAR before we've configured the global interrupt number offset for the PSI interrupts. If any PSI interrupt is we'll send an interrupt trigger notification to the XIVE with the wrong interrupt vector (0..15). This can potentially cause a checkstop since there may not be an EAS / IVT configure for that vector. Fix this by registering and masking all the PSI interrupts after we've configured the ESB BAR, but before configuring the notification address and offset. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
generated by cgit v1.1 at 2024-08-02 16:37:19 +0000