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AgeCommit message (Expand)AuthorFilesLines
2021-08-06hw/chiptod: Abort if core frequency is not setVasant Hegde1-0/+6
2021-08-06hw/chiptod: Retry the sync procedure on failureRyan Grimm1-10/+23
2021-08-06xive2: Add NCU_SPEC_BAR to stop engine for restoreVaidyanathan Srinivasan1-3/+24
2021-08-06libpore: P10 stop-api supportPratik Rajesh Sampat1-4/+82
2021-08-06phb5: Fix PHB max link speed definition on P10Frederic Barrat1-2/+2
2021-08-06phb4/5: Fix PHB link width detection to avoid useless retrainingsFrederic Barrat1-11/+80
2021-08-06phb4: Cleanup PEC config discovery in CAPI modeFrederic Barrat1-8/+9
2021-08-06phb5: Workaround for PCI bug HW551382Frederic Barrat1-0/+35
2021-08-06phb5: Enable Gen5Michael Neuling1-4/+8
2021-08-06phb5: Add register inits specific to Gen5Frederic Barrat1-5/+13
2021-08-06phb5: Activate StoreEOI for LSIsCédric Le Goater1-1/+1
2021-08-06xive/p10: Change alignment of the queue overflow pagesCédric Le Goater1-2/+18
2021-08-06xive/p10: Tune max_entries_in_modified when split_mode is onCédric Le Goater1-0/+1
2021-08-06xive/p10: Activate has_array when PQ_disable is availableCédric Le Goater1-3/+8
2021-08-06xive/p10: Activate split mode for PHB ESBs when PQ_disable is availableCédric Le Goater1-0/+25
2021-08-06xive/p10: Introduce a new OPAL_XIVE_IRQ_STORE_EOI2 flagCédric Le Goater1-1/+1
2021-08-06xive/p10: Add automatic Context Save and Restore supportCédric Le Goater1-0/+48
2021-08-06xive/p10: Configure XIVE for fused coresCédric Le Goater1-1/+16
2021-08-06hw/psi-p10: Configure interrupt offset before notify addrOliver O'Halloran1-10/+10
2021-08-06xive/p10: Introduce new capability bitsCédric Le Goater2-9/+51
2021-08-06psi/p10: Mask all sources at initCédric Le Goater1-0/+7
2021-08-06psi/p10: Introduce xive2_source_mask()Cédric Le Goater2-1/+17
2021-08-06hw/phb5: Add support for 'Address-Based Interrupt Trigger' modeCédric Le Goater2-12/+57
2021-08-06hw/phb5: Add support for PQ offloadingCédric Le Goater2-10/+77
2021-08-06xive/p10: Add option flags to the XIVE exploitation modeCédric Le Goater1-7/+22
2021-08-06hw/phb5: Add initial supportJordan Niethe3-76/+183
2021-08-06psi/p10: Activate StoreEOICédric Le Goater1-1/+14
2021-08-06psi/p10: Activate 64K ESB pagesCédric Le Goater1-3/+4
2021-08-06xive/p10: Add a XIVE2 driverCédric Le Goater5-9/+4479
2021-08-06platform: Add Denali platform supportVasant Hegde1-0/+1
2021-08-06hw/imc: Power10 supportAnju T Sudhakar2-10/+56
2021-08-06hw/nx: Enable p10 DARNRyan Grimm1-7/+22
2021-08-06NX: Set VAS RMA write BAR register on P10Haren Myneni2-0/+54
2021-08-06VAS: Enable VAS on P10Haren Myneni1-5/+24
2021-08-06VAS: Define Remote Memory Access paste address on P10Haren Myneni1-3/+73
2021-08-06hw/phys-map/p10: Add P10 MMIO mapAlistair Popple2-4/+101
2021-08-06prd: Add base P10 supportOliver O'Halloran1-0/+5
2021-08-06phys/P10: Use topology index to get phys mappingVasant Hegde2-3/+22
2021-08-06occ: Add POWER10 supportVaidyanathan Srinivasan3-14/+165
2021-08-06psi/p10: Activate P10 interruptsCédric Le Goater1-1/+63
2021-08-06Basic P10 stop state supportVaidyanathan Srinivasan2-16/+126
2021-08-06hw/chiptod: Add POWER10 supportNicholas Piggin1-15/+59
2021-08-06hw/p8-i2c: Add POWER10 supportOliver O'Halloran1-15/+14
2021-08-06Initial POWER10 enablementNicholas Piggin4-11/+58
2021-08-04POWER9 Cleanups: Don't force clear SPW bitsPratik R. Sampat1-9/+5
2021-07-19powercap: occ: Set occ_set_powercap as const attributePratik R. Sampat1-1/+1
2021-07-19hw/imc: Refactor trace-imc macrosMadhavan Srinivasan1-11/+19
2021-06-30hw/imc: Do scoms on the secondary core in fused core mode for core-imc countersAnju T Sudhakar1-63/+90
2021-06-30hw/imc: Use the xscom macros for IMC based on platformAnju T Sudhakar1-34/+61
2021-06-30hw/imc: Cleanup code to define scom addr for IMC at run timeAnju T Sudhakar1-2/+32
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