Age | Commit message (Collapse) | Author | Files | Lines |
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free() asserts because local_alloc() doesn't allocate from the skiboot
heap region. Fix this by using local_free().
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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The documented PEC recovery procedure is to clear the PEC FIR
registers when the ETU/PHB is in reset. However, any xscom access
targeting a PHB register while it is in reset will raise a new
error (PFIR bit 3), so it is possible to get out of reset and still
have a FIR register showing errors. It has been observed that the OCC,
through its 24x7 service, can do such a xscom access at boot time if
we end up in the CRESET path. So the current behavior of logging an
error is not desirable.
The recommendation from the logic designer is to keep the existing
mechanism to clear the FIR registers and add an extra step to clear
any new errors immediately after taking the ETU out of reset. That's
what this patch is doing.
Fixes: https://github.com/open-power/skiboot/issues/273
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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This patch improves readability just a tiny bit by using symbols, most
of them already existing, instead of values when accessing the PEC
registers.
No functional changes.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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When looking for which interrupts are serviced by opal, we scan all
sources and query every single interrupt to know if it's for linux or
opal. An optimization was made so that if the source doesn't have an
'interrupt' op (=the handler) or an 'attributes' op (to do the
query), then we can skip the source. That's all good.
However, when xive was introduced, the 'irq_source' defining those ops
was wrapped in a 'xive_src' source which adds a level of indirection
for those 'attributes' and 'interrupt' ops. So the previous
optimization no longer works: the 'attributes' and 'interrupt' ops are
defined from the wrapper, but if we could look past the indirection,
we would realize they are not.
That is getting problematic for the rather large generic IPIs
source. We have 8 million such interrupts defined per chip on P10 and
because the above optimization is no longer kicking in, we are now
querying every single one of them to know if it is for opal. Real
hardware swallows it without much difficulty, but simulators
don't. Running qemu on my laptop, the full scan takes ~12 seconds per
chip!
This patch adds a callback for an interrupt source to report whether
it has opal interrupts. If the source doesn't define it, then we
fallback to looking at the 'interrupt' and 'attributes' ops, like
before, as it is still useful on P8. We can then define that new
callback on the xive sources, allowing to look past the indirection
level and skip scanning the source when appropriate.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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There's no reason to skip 2 bits when printing the Notification Source
Register (NSR) of any thread context ring. So it's got to be a silly
mistake and we should shift by 56 bits and not 58 :-)
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Dan Horák <dan@danny.cz>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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Caught by CI in fedora-rawhide (GCC 12):
hw/fsp/fsp-codeupdate.c:116:26: error: '%s' directive argument is null [-Werror=format-overflow=]
116 | prlog(PR_NOTICE, "CUPD: IPL SIDE = %s\n", side);
To prevent this, explicitly print the value of ipl_side instead.
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Reviewed-by: Dan Horák <dan@danny.cz>
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Use a look up table to support the p9, p10dd1 and p10dd2 conversions.
Running on a Rainier:
> [ 268.267370706,6] CPU: P10 generation processor (max 4 threads/core)
> [ 268.267372501,7] CPU: Boot CPU PIR is 0x0460 PVR is 0x00801200
> [ 268.284420384,5] CHIP: Chip ID 0000 type: P10 DD2.02
> [ 268.284464084,5] CHIP: Chip ID 0002 type: P10 DD2.02
> [ 268.284500468,5] CHIP: Chip ID 0004 type: P10 DD2.02
> [ 268.284538166,5] CHIP: Chip ID 0006 type: P10 DD2.02
> [ 268.286317879,5] PLAT: Detected Rainier platform
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Dan Horák <dan@danny.cz>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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In preparation for adding p10 logic. No functional change.
Reviewed-by: Dan Horák <dan@danny.cz>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
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Resolves : the warray bounds warning during compilation
/build/libc/include/string.h:34:16: warning: '__builtin_memset' offset [0, 2097151] is out of the bounds [0, 0] [-Warray-bounds]
34 | #define memset __builtin_memset
hw/fsp/fsp.c:1855:9: note: in expansion of macro 'memset'
1855 | memset(fsp_tce_table, 0, PSI_TCE_TABLE_SIZE);
use volatile pointer to avoid optimization introduced with gcc-11 on constant
address assignment to pointer.
Signed-off-by: Abhishek Singh Tomar <abhishek@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Make the P8 NPU code depend on CONFIG_P8. This requires converting
a low level function to a no-op because the HMI NPU handling is not
so cleanly layered.
This saves an extra 6kb of skiboot.lid.xz.
Reviewed-by: Dan Horák <dan@danny.cz>
Signed-off-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Convert VAS and NX to use the hwprobe facility for init.
Reviewed-by: Dan Horák <dan@danny.cz>
[npiggin: remove imc_init because it moved later in boot (fbcbd4e47c)]
Signed-off-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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POWER8 support is large and significantly different than P9/10 code.
This change prepares to make P8 support configurable.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[ clg: Removed commented headers in slw.c ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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This saves about 10kB from skiboot.lid.xz
Reviewed-by: Dan Horák <dan@danny.cz>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Rather than have code call processor-specific SBE routines depending
on version, hide those details in SBE APIs.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[ clg: Fixed run-timer test ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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We can use a base CPU of POWER9 if we don't have P8.
We can also hide PHB3 code behind this,
and shave 12kb off skiboot.lid.xz
Reviewed-by: Dan Horák <dan@danny.cz>
[npiggin: add cpp define, fail gracefully on P8]
Signed-off-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Reviewed-by: Dan Horák <dan@danny.cz>
[npiggin: split out from initial hwprobe pach]
Signed-off-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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The existing sequence writes TBU twice and leaves TBL unchanged. This
may not really matter if it's being resynced from the chiptod soon, but
it's possible it could clear a parity error.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Compilation can fail when building tests if the opal-api.h include
is not pulled in via headers. Include it directly.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Upstream ccan uses (list, existing entry, new entry) parameter ordering
rather than (list, new entry, existing entry) ordering.
Switch these to make syncing with upstream simpler.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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This patch fixes errors seen when linux looks for the interrupt to use
for a device LSI:
pci X:Y:Z of_irq_parse_pci: failed with rc=-22
The of/irq parsing code requires those new properties to be able to
map the interrupt specifier correctly. It was not needed before
comitting cd12ea6d8e1 ("interrupts: Do not advertise XICS support on
P10"), because the LSI mapping code was defaulting to the XICS
interrupt controller node, which is now removed (and had those
properties).
Fixes: cd12ea6d8e1 ("interrupts: Do not advertise XICS support on P10")
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Lowest Point of Coherency (LPC) memory allows the host to access memory on
an OpenCAPI device.
When the P10 chip accesses memory addresses on the AFU, the Real Address
on the PowerBus must hit a BAR in the PAU such as GPU-Memory BAR. The BAR
defines the range of Real Addresses that represent AFU memory.
The two existing OPAL calls, OPAL_NPU_MEM_ALLOC and OPAL_NPU_MEM_RELEASE
are used to manage the AFU momory.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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The remaining translation mode: OpenCAPI 5.0 with TLBI/SLBI Snooping, is
not used due to performance problems caused by the mismatch between the
ERAT and Bloom Filter sizes.
When the Address Translation Mode requires TLB and SLB Invalidate
operations to be initiated using MMIO registers, a set of registers like
the following is used:
• XTS MMIO ATSD0 LPARID register
• XTS MMIO ATSD0 AVA register
• XTS MMIO ATSD0 launch register, write access initiates a shoot down
• XTS MMIO ATSD0 status register
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Update the content of three current OPAL API calls to support PAU.
- OPAL_NPU_SPA_SETUP
The Shared Process Area (SPA) is a table containing one entry (a
"Process Element") per memory context which can be accessed by the
OpenCAPI device.
- OPAL_NPU_SPA_CLEAR_CACHE
The PAU keeps a cache of recently accessed memory contexts. When a
Process Element is removed from the SPA, the cache for the link must
be cleared.
- OPAL_NPU_TL_SET
The Transaction Layer specification defines several templates for
messages to be exchanged on the link. During link setup, the host
and device must negotiate what templates are supported on both sides
and at what rates those messages can be sent.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Add elementary functions to handle a phb complete, fundamental and
hot resets.
For the time being, specific creset and hreset are not supported.
A complete fundamental reset is based on the following steps, in this
order:
- Place all bricks into Fence state
- Disable BARs
- Reset ODL to Power-on Values
- Set the i2c reset pin in output mode
- Initialize PHY Lanes
- Deassert ODL reset
- Clear the the i2c reset pin
- Unfence bricks
- Enable BARs
- Enable ODL training mode
Link training is also set up.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Follow the Procedure IO_INIT_RESET_PON as described in the
P10 OPHY workbook document to reset and initialize the PHY lanes.
The memory mapped SRAM (64 bit aligned) has to be used to configure the
PHY, which is reachable the linked registers: address and data.
The different links can be configured at the same time, that implies using
a global lock to avoid conflicts.
Authored-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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This patch add a new function to dump PAU registers when a HMI has been
raised and an OpenCAPI link has been hit by an error.
For each register, the scom address and the register value are printed.
The hmi.c has been redesigned in order to support the new PHB/PCIEX
type (PAU OpenCapi). Now, the *npu* functions support NPU and PAU units of
P8, P9 and P10 chips.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Add more PHB interfaces:
- to control pci error type in case of freeze.
- add the addresses of the registers needed by the OS to handle
translation failures.
- to detect the fence state of a specific brick
- to configure BDF (Bus Device Function) and PE (Partitionable Endpoint)
for context identification.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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The default action for the errors (unexpected errors on the opencapi
link) reported in the PAU FIR2 registe is mostly set to system
checkstop.
This patch changes the default action of those errors so that the PAU
will raise an interrupt instead. Interrupt information are logged so
that the error can be debugged and linux can catch the event.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Next main part of the hypervisor PAU initialization.
The P10 PAU supports two OpenCAPI links.
The PAU provides various configuration selections for both of the OCAPI
Link Transaction Layer functions (OTLs). These include a link enable,
behavior controls, debug modes, and virtual channel credits to send to
the AFU. The OTL Configuration 0, OTL Configuration 1, OTL
Configuration 2, and TLX Credit Configuration registers are used to
control these functions.
This patch completes the PAU configuration following the
sections 17.1.3.4 to 17.1.3.10.2 of the workbook document.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Enable OpenCAPI mode for each brick which are connected to be used in
this mode. This is be done through 7 steps as described in the
P10 OCAPI 5.0 Processing Unit Workbook document, section:
17.1.3.1 Enabling OpenCAPI.
The following sequences must be performed:
1. Set Transport MUX controls to select OpenCAPI
2. Enable Clocks in XSL
3. Enable Clocks in MISC
4. Set NPCQ configuration
5. Enable XSL-XTS Interfaces
6. Enable State-machine allocation
Enabling the NTL/GENID BARS allows to access to the MMIO registers.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Implement the necessary operations for the OpenCAPI PHB type and
inform the device-tree properties associated.
The OpenCapi PCI config Addr/Data registers are reachable through
the Generation-ID Registers MMIO BARS.
The Config Address and Data registers are located at the following offsets
from the AFU Config BAR plus 320 KB.
• Config Address for Brick 0 – Offset 0
• Config Data for Brick 0 – Offsets:
◦ 128 – 4-byte config register
• Config Address for Brick 1 – Offset 256
• Config Data for Brick 1 – Offsets:
◦ 384 – 4-byte config register
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Configure early PAU Global MMIO BAR registers to allow PAU MMIO
register accesses. This is done for each PAU. Enable the Powerbus
interface is mandatory for MMIO accesses.
For each OpenCAPI device, configure the bar registers to access to
the AFU MMIO and to the AFU Config Addr/Data registers.
AFU Config/Data registers = GENID_ADDR (from phy_map file) + 320K
(= 0x50000)
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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OpenCapi for P10 is included in the P10 chip. This requires OCAPI capable
PHYs, Datalink Layer Logic and Transaction Layer Logic to be included.
The PHYs are the physical connection to the OCAPI interconnect.
The Datalink Layer provides link training.
The Transaction Layer executes the cache coherent and data movement
commands on the P10 chip.
The PAU provides the Transaction Layer functionality for the OCAPI
link(s) on the P10 chip.
The P10 PAU supports two OCAPI links. Six accelerator units PAUs are
instantiated on the P10 chip for a total of twelve OCAPI links.
This patch adds PAU opencapi structure for supporting OpenCapi5.
hw/pau.c file contains main of PAU management functions.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Move the OPAL entry points for npu2 opencapi to the common opal NPU
file. This prepares us to add same entries for PAU opencapi in this common
file.
No functional change.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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This patch enables Skiboot to initialize and Linux to boot to user space
on the AWAN core and chip models.
We need the distinction between core and chip models because the core
models do not have an XSCOM unit, CHIPTOD, nor RNG. The chip
model does have them and they work.
So, add a device_type property to the awan node to distinguish core from
chip. Sample DTS are provided for the core and chip models in
external/awan.
Just like Mambo, we need to return in slw_init before trying to
initialize SLW. Without an XSCOM unit in the device tree for the core
model, the SLW code path eventually fails an assert due to lack of
chips.
This commit defines a QUIRK_AWAN where previously Mambo used
QUIRK_MAMBO_CALLOUTS so now Mambo and AWAN core both work.
Also, fix up chip quirks so the core model and chip model boot and
initialize the appropriate units.
Disable sreset and power management in a couple spots because the chip
model does not support stop with EC=1 and enter_p9_pm_state spins in the
branch-to-self after stop.
Provide an external/awan/README.md with a high-level view of booting in
the environment.
Signed-off-by: Ryan Grimm <grimm@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Fix endian for the 4-byte LPC copy similarly to other flash drivers.
This allows flash to be detected on POWER8 AST BMC systems with a LE
skiboot.
Fix incorrect comments in those other drivers while we're here.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Convert phb3 dt construction and in-memory hardware tables to use
explicit endian conversions.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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This significantly simplifies the SLW code.
HILE is now always supported.
Reviewed-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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On P10, get_ics_phandle() calls xive2_get_phandle() directly. This
results in a NULL dereference on mambo when xive2 is not set up.
This was caught with the virtual memory boot patch on P10 mambo.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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This patch removes the following properties from PHB entries in the
device tree on P10, since there's no CAPP any more and the properties
no longer make sense:
ibm,phb-indications
ibm,capp-timebase-sync
ibm,capi-flags
It has no effect on linux: some were already ignored and others won't
even be read since the cxl driver (the only consumer) already fails
early on P10.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Update PVR and mambo f000f bits:
- Set POWER10 to DD2.0
Update SIM_CTRL and SIM_CTRL1 bits:
- Set the LPAR-per-core mode bit. This is required for SMT KVM to work.
- Set ARC0/ARC1 bits which enable atomic RC update interrupts (not
hardware updates), which matches implementation.
- Enable DEXCR, HAIL, ROP, BHRB disable, block BHRB writes in PR=0,
and RFC02628 on POWER10.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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npu3 was only used on the Swift platform to add support for
GPUs (nvlink). The Swift platform has never left the lab and support
for GPUs on it is pretty much dead. So let's remove it.
The patch removes all related code. Device tree entries are no
longer created and in the very unlikely case that someone is still
trying to boot it, the linux nvlink discovery code should be quiet.
Tested by booting on Swift with no GPU.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Reza Arbab <arbab@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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An hw issue was found on P10 (HW560152) where a page-level TCE kill
can be dropped if there are enough TCE kill requests already being
processed. The net effect is that data integrity is not
guaranteed. The circumvention is to stay away from page-level kills
and escalate those to PE kills. Which hurts performance.
It also affects P9.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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We only support the XIVE interface.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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HW has some reserved fields which break the comparison when checking
END cache updates.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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The special cache check done when skiboot is compiled with DEBUG is
incompatible with Automatic Context Save and Restore.
Random data is written in the NVP to check that cache updates are
correct but this can lead to a checkstop raised by the XIVE interrupt
controller. When the NVP Valid (0) bit, the hardware controlled H (7)
bit, and the Checked Out bit (45) are all ones at the same time, the
HW thinks that the NVP entry is checked out by a thread and does not
allow the cache write to occur.
Make sure that the valid bit is not set on the NVP.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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The chiptod sync will sometimes fail and then sync successfully after a
retry. So, try an arbitrary 10 numbers of times before we either
abort() on main procedure fail or disable threads on secondary procedure
fail. Also, put a message on the log if secondaries fail so we have
evidence in the log when they aren't enabled.
Signed-off-by: Ryan Grimm <grimm@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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P10 Stop engines have apis similar to P9 to set xscom restores
after wakeup from deep-sleep states.
This xscom restore will be used to support STOP11 on P10.
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com>
Signed-off-by: Pratik Rajesh Sampat <psampat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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