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2017-01-04console: remove con_ops->flush()Oliver O'Halloran1-3/+0
Flushing the OPAL console is now handled by a driver specific OPAL call handler so this can be removed. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-01-04console: use opal_con_ops APIOliver O'Halloran2-13/+3
Adds a new structure that contains the implementations of the various OPAL console handlers. This is intended to replace the existing ad-hoc mechanism where the OPAL call handlers are overwritten in the OPAL console driver's init function. Currently this just moves the site where the OPAL call handlers are overwritten to inside of console.c, but it is intended to give us a mechanism for implementing features such as pointer validation for the OPAL console calls without having to manually update each driver. This also helps to clarify differences between the internal (skiboot) console and the external (OPAL) console. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-01-04console: add opal_con_ops structureOliver O'Halloran2-0/+32
Adds a separate structure to house the operations for the OPAL console. This is used to define a new API for dealing with the OPAL console in the next patch. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-01-04console: add helper to create serial console nodesOliver O'Halloran2-30/+10
The creation of /ibm,skiboot/console/serial@<xyz> nodes is pretty much identical across the various OPAL console drivers. This patch moves it into a helper function as a cleanup. Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-01-04console: don't use __flush_console() outside console.cOliver O'Halloran1-1/+1
There is only one use of this function outside of console.c and that usage is broken. As the name suggests this is an internal function that is only safe when the console lock held is held. flush_console() will acquire the lock for the caller so that should be used instead. Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-12-22phb3: Lock the PHB on set_xive callbacksBenjamin Herrenschmidt1-0/+8
Those are called by the interrupts core and thus skip the locking implicit in the PCI opal calls. However IODA table access can be racy, so make sure we lock the PHB. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-12-21tree-wide: use dt_add_property_u64s() where we canOliver O'Halloran6-17/+7
A few places (mostly old code) were using: add_property_cells(hi32(number), lo32(number)); This patch converts them to use the helper rather than doing it manually. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-12-21Always set ibm,occ-functional-state correctlyPridhiviraj Paidipeddi1-6/+13
Currently chip->occ_functional data field set's to true always whether ibm,occ-functional-state property exists or not. ibm,occ-functional-state property of xscom node's are populated only in ibm,fsp systems by detecting the OCC state in OPAL/SPIRA. In non-fsp(i.e OpenPower) systems this property is not populating. But OPAL sets chip->occ_functional field incorrectly to true without acually knowing the occ state. OCC Spec says: When OCC is told to go active it will populate OCC-OPAL shared memory interface with ‘valid’ and all Pstate data. So incase of OpenPower systems OPAL can add DT property ibm,occ-functional-state and set the chip->occ_functional when OPAL finds the valid homer region and corresponding occ_valid byte is set to 0x1. Signed-off-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: squash commits, tweak commit message] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-12-16psi: fix the xive registers initialization on P8Cédric Le Goater1-12/+8
When skiboot initializes PSIHB, it fills the xive registers with server=0, prio=0xff. The source (irq) value is left shifted by 29 bits and the last two xive registers (irq 4 and 5) are set with a bogus value : write 0x30 val 0x000000ff00000000 write 0x60 val 0x000000ff20000000 write 0x68 val 0x000000ff40000000 write 0x70 val 0x000000ff60000000 write 0x78 val 0xffffffff80000000 write 0x80 val 0xffffffffa0000000 which seems to be fine for real HW but causes a lof of pain under qemu. Let's use an 'unsigned' type to initialize the xive registers and also use a loop on the PSI irq numbers, like it is done in psi_cleanup_irq. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-12-14pci: Always print PHB and PE numbers as hexadecimalRussell Currey3-23/+23
PHB and PE numbers are sometimes printed as decimal and sometimes as hexadecimal, which is confusing. Standardise on hexadecimal. This is especially useful now that PHB numbers in Linux always match their OPAL ID. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-12-13slw: Set PSSCR value for idle statesShilpasri G Bhat1-14/+78
PSSCR(Processor Stop Status and Control Register) is an SPR whose contents control the operation of stop instruction. Currently in DT, the value of PSSCR only included RL(Requested Level) for each idle state. This patch adds MTL(Maximum Transistion Level), TR(Transistion Rate), ESL(Enable State Loss) and EC(Exit Criterion) bits for idle state in the PSSCR configuration. It also adds new idle states stop0_lite, stop1_lite and stop2_lite which are no state loss versions of stop0, stop1 and stop2 respectively. The lite variant has EC and ESL bits of PSSCR set to 0. The thread entering a lite variant of stop state will not lose any state and will wakeup at next instruction following stop if MSR.EE=0 or at the corresponding interrupt handler if MSR.EE=1. This will reduce the exit latency of the idle state and hardware will not allocate the thread resources to other threads while in power saving mode. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-12-13mambo: Add Fake NVRAM driverJack Miller2-0/+63
Implement a fake NVRAM device based on arbitrary memory reserves. This allows NVRAM images to be preloaded without the FSP. Signed-off-by: Jack Miller <jack@codezen.org> Tested-by: Chris Smart <chris@distroguy.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-12-13hw/phb3: fix error handling in complete resetAndrew Donnellan1-2/+1
During a complete reset, when we get a timeout waiting for pending transaction in state PHB3_STATE_CRESET_WAIT_CQ, we mark the PHB as permanently broken. Set the state to PHB3_STATE_FENCED so that the kernel can retry the complete reset. Reported-by: Pradipta Ghosh <pradghos@in.ibm.com> Suggested-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-12-08sensor: add a family field in the handlerCédric Le Goater2-4/+4
Currently, we are hijacking the last bit of the resource field of the sensor handler to differentiate the sensor families and route the opal_sensor_read() call to the appropriate component. Let's reserve the last 3bits and provide an API to set the sensor family for current use and future use. This gives us a maximum of 8 families and 32 resource classes. The FSP uses 15, so we should be fine for a while. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-12-08phb3: Trick to allow control of the PCIe link width and speedBenjamin Herrenschmidt1-0/+86
This implements a hook inside OPAL that catches 16 and 32 bit writes to the link status register of the PHB. It allows you to write a new speed or a new width, and OPAL will then cause the PHB to renegociate. Example: First read the link status on PHB4: setpci -s 0004:00:00.0 0x5a.w a103 It's at x16 Gen3 speed (8GT/s) bits 0x0ff0 are the width and 0x000f the speed. The width can be 1 to 16 and the speed 1 to 3 (2.5, 5 and 8GT/s) Then try to bring it down to 1x Gen1 : setpci -s 0004:00:00.0 0x5a.w=0xa011 Observe the result in the PHB: / # lspci -s 0004:00:00.0 -vv 0004:00:00.0 PCI bridge: IBM Device 03dc (prog-if 00 [Normal decode]) .../... LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive+ BWMgmt- ABWMgmt+ And in the device: / # lspci -s 0004:01:00.0 -vv .../... LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-12-02p8-i2c reset things manually in some error conditionsStewart Smith1-22/+157
It appears that our reset code wasn't entirely correct, and what we're meant to do is reset each port and wait for command complete. In the event where that fails, we can then bitbang things to recover to a state where at least the i2c engine isn't in a weird state. Practically, this means that "i2cdetect -y 10; i2cdetect -y 10" (where 10 is the bus where a TPM is attached, typically p8e1p2) doesn't hard lock the machine (things are still bad and you won't reboot successfully, but it's *better*). one downside to this patch is that we spend a *long* time in OPAL (tens of ms) when doing the reset. This is something that we really need to fix, as it's not at all nice. The full fix for this though will involve changing a decent chunk of the p8-i2c code, as we don't want to write *any* registers while doing this extended reset (while existing code checks status a bit later). Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-30phb4: Add ability to log config space accessMichael Neuling1-0/+13
Useful for debugging Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-24p8i2c: Use calculated poll_interval when booting OPALStewart Smith1-10/+13
Otherwise we'd default to 2seconds (TIMER_POLL) during boot on chips with a functional i2c interrupt, leading to slow i2c during boot (or hitting timeouts instead). Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-24slw: do SLW timer testing while holding xscom lockStewart Smith2-9/+29
We add some routines that let a caller get the xscom lock once and then do a bunch of xscoms while holding it. In some situations without this, it could take long enough to get the xscom lock that the 1ms timeout would expire and we'd falsely think the SLW timer didn't work when in fact it did. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-24i2c: Add i2c_run_req() to crank the state machine for a requestStewart Smith1-0/+18
Doing everything asynchronously is brilliant, it's exactly what we want to do. Except... the tpm driver wants to do things synchronously, which isn't so cool. For reasons that are not yet completely known, we spend an awful lot of time in the main thread *not* running pollers (potentially seconds), which doesn't bode well for I2C timeouts. Since the TPM measure is done in a secondary thread, we do *not* run pollers there either (as of 323c8aeb54bd4e0b9004091fcbb4a9daeda2f576 - which is roughly as of skiboot 2.1.1). But we still need to crank the i2c state machine, so we introduce a call to do just that. It will return how long the poll interval should be, so that we can time_wait() for a more appropriate time for whatever i2c implementation is sitting behind things. Without this, it was "easy" to get to a situation where the i2c state machine wasn't cranked at all, and you'd hit the i2c timeout (for the issued operation) before the poller to crank i2c was ever called. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> Tested-by: Claudio Carvalho <cclaudio@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-24fsp: Don't recurse pollers in ibm_fsp_terminateStewart Smith2-1/+38
If we were to terminate in a poller, we'd call op_display() which called pollers which hit the recursive poller warning, which ended in not much fun at all. This patch will skip the running of pollers and instead run the FSP poller to set the op-panel display before attn. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-24phb4: Change debug printsMichael Neuling1-18/+20
Currently we print "PHB4" and mean either "PHB version 4" or "PHB number 4" which can be quite confusing. This makes it clearer when it's one or the other. Also fixes some cut and paste errors in comments from PHB3. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-24phb4: Fix config space enable bits on DD1Michael Neuling1-0/+3
Fix enabling config space on DD1. Without this PCI devices disappear on kexec. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-24phb4: Fix location of EEH enable bitsMichael Neuling1-1/+1
Fix some of the bit definitions. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15chiptod: More hardening against -1 chip IDBenjamin Herrenschmidt1-0/+6
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15phb4: Fix setting of max link speedBenjamin Herrenschmidt1-2/+3
Make sure we set consistent values between Init_4 and Init_14 and set the default to Gen4 not Gen3 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15phb4: Updated inits as of PHB4 spec 0.52Benjamin Herrenschmidt1-27/+51
This includes some DD2.0 support Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15xive: Indirect table entries must have top bits "type" setBenjamin Herrenschmidt1-0/+3
The HW check that the 2 tops bits aren't both clear to differenciate an unallocated entry from a valid one. So we need to put some value there. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15xive: Remove unused field and clarify commentBenjamin Herrenschmidt1-4/+1
This will be reworked when we support EQ and VP allocation, for now remove the unused field Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15xive: Provide a way to override some IPI sourcesBenjamin Herrenschmidt3-24/+52
Some devices such as NX or the NPU will use some of the XIVE provided IPIs for their own interrupts. Thus we need a way for those to provide a custom irq_source_ops for portions of the IPI space in order for them to provide their own attributes() and if needed, interrutps() callbacks. We achieve that by creating a second list of sources which can overlap the primary. The global stock of IPIs is registered by XIVE in the secondary list which is searched when no match is found in the primary. A new API xive_register_ipi_source() is provided for those devices to create an overlapping source structure in the primary list for a subset of the IPIs. Those IPIs must have been previously allocated using xive_alloc_ipi_irqs() Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15xive: Add helper to retrieve an IPI trigger portBenjamin Herrenschmidt1-0/+19
To be used by such things as VAS Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15xive: Fix IPI EOI logic in opal_xive_eoi()Benjamin Herrenschmidt1-9/+9
We only want to directly EOI the interrupt used to emulate the MFRR, for all the other "IPI" (aka XIVE produced interrupts), we want to go via the normal source mechanism. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15xive: Don't try to EOI a masked sourceBenjamin Herrenschmidt1-0/+12
It will just generate spurious powerbus traffic and ESB state changes. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15xive: Fix comments in xive_source_set_xive()Benjamin Herrenschmidt1-6/+16
Properly documenting assumptions and behaviour related to interrupts occurring while masked. This reflects the documentation update. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15xive: Fix comments in xive_get_ive()Benjamin Herrenschmidt1-6/+3
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15xive: Configure forwarding portsBenjamin Herrenschmidt1-2/+40
In multi-chip environments, the XIVEs need to communicate to each other via these ports, so they need to be configured properly Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15xive: Fix mangling of interrupt server# in opal_get/set_xive()Benjamin Herrenschmidt1-7/+5
The OPAL API uses mangled server numbers with the link in the bottom 2 bits like a real XICS does, we need to account for it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15xive: Fix interrupt number manglingBenjamin Herrenschmidt1-3/+3
The comment and implementation didn't match, we were putting the block_id in the part of the field reserved for the CPPR. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15psi: Fix P9 BAR setup on multi-chipsBenjamin Herrenschmidt1-2/+4
We need to inject the chip id in the MMIO address Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15psi: Add DT option to disable LPC interruptsBenjamin Herrenschmidt1-1/+22
Some sim models have the LPC interrupts stuck asserted on secondary chips so we add a device-tree option that makes us set the policy for these to "Linux" instead of "OPAL". Since they aren't referenced in the device-tree this will de-facto prevent them from being enabled Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-08bmc_platform: fail PNOR access request if no bmc *before* we reserve itStewart Smith1-4/+3
Fixes: 5611389876a748e19b7593d4eb426ced7a6ed31f Reported-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-08Add BMC platform to enable correct OEM IPMI commandsStewart Smith1-2/+19
An out of tree platform (p8dtu) uses a different IPMI OEM command for IPMI_PARTIAL_ADD_ESEL. This exposed some assumptions about the BMC implementation in our core code. Now, with platform.bmc, each platform can dictate (or detect) the BMC that is present. We allow it to be set at runtime rather than purely statically in struct platform as it's possible to have differing BMC implementations on the one machine (e.g. AMI BMC or OpenBMC). Acked-by: Jeremy Kerr <jk@ozlabs.org> [stewart@linux.vnet.ibm.com: remove enum, update (C) years] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-08hw/ipmi-sensor: Fix setting of firmware progress sensor properly.Pridhiviraj Paidipeddi1-2/+42
Currently Hostboot populates /bmc/sensors dt node and corresponding sensors only for BMC platforms, And for FSP platforms hostboot is not populating any fsp sensors(Management sensors) and also there is no firmware progress sensor exist in fsp platforms. Due to which OPAL incorrectly setting firmware status on a sensor id "00" which is not at all exist. On a FSP system: cat /sys/firmware/opal/msglog | grep -i setting [ 21.189204883,6] IPMI: setting fw progress sensor 00 to 07 [ 21.189559121,6] IPMI: setting fw progress sensor 00 to 13 cat /sys/firmware/opal/msglog | grep -i skiboot [ 84.127416495,5] SkiBoot skiboot-5.4.0-rc3 starting... On a BMC system: cat /sys/firmware/opal/msglog | grep -i setting [ 3.166286901,6] IPMI: setting fw progress sensor 05 to 14 [ 14.259153338,6] IPMI: setting fw progress sensor 05 to 07 [ 14.469070593,5] IPMI: Resetting boot count on successful boot [ 15.001210324,6] IPMI: setting fw progress sensor 05 to 13 So this patch fixes this incorrect setting on a fsp system, and also sets the sensor only if OPAL initialises ipmi sensors and corresponding sensor exists for a given sensor type in the device tree. After patch: On a FSP system: cat /sys/firmware/opal/msglog | grep -i setting On a BMC system: cat /sys/firmware/opal/msglog | grep -i setting [ 3.164859816,6] IPMI: setting fw progress sensor 05 to 14 [ 14.024941077,6] IPMI: setting fw progress sensor 05 to 07 [ 14.211514767,5] IPMI: Resetting boot count on successful boot [ 14.252554375,6] IPMI: setting fw progress sensor 05 to 13 Signed-off-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: return OPAL_UNSUPPORTED on !sensors_present, make ipmi_sensor_type_present() static in ipmi-sensor.c] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-10-25errorlog: Removal of elog_reject_head() from 'opal_kexec_elog_notify' routineMukesh Ojha1-1/+0
elog_reject_head() routine makes the state 'elog_read_from_fsp_head_state' either 'ELOG_STATE_REJECTED' or 'ELOG_STATE_NONE' depending on the current state of 'elog_read_from_fsp_head_state'. We can remove this elog_reject_head() from 'opal_kexec_elog_notify()' as just after that it is called inside 'fsp_opal_resend_pending_logs()'. So, it is redundant inside opal_kexec_elog_notify() routine. Signed-off-by: Mukesh Ojha <mukesh02@linux.vnet.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-10-25errorlog: Remove the elog enable check from 'fsp_elog_check_and_fetch_head'Mukesh Ojha1-3/+0
We use 'elog_enabled' flag to check whether host OS is ready to receive error log or not. This is nothing to do with reading error log from service processor. This patch is to remove the check and keep this 'elog_enabled' free from FSP specific code and move it into core/errorlog.c in later upcoming patches. With this changes, in some corner cases we may endup reading same error log twice from FSP. It happens as we call 'elog_reject_head' inside 'fsp_opal_resend_pending_logs' which makes the state either 'ELOG_STATE_REJECTED' or 'ELOG_STATE_NONE'. So, a call to 'fsp_elog_check_and_fetch_head' routine ends up reading the error log from FSP which was already read. This case happens twice in a reboot as whenever 'fsp_opal_resend_pending_logs' gets called. So, we can ignore it. Signed-off-by: Mukesh Ojha <mukesh02@linux.vnet.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-10-25errorlog : Modification as per coding guidelines to make the code more legibleMukesh Ojha3-173/+188
Some modifications related to typo errors, alignment, case letter mismatch to add more clarity to the code. Signed-off-by: Mukesh Ojha <mukesh02@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-10-25fast-reboot: disable on FSP code update or unrecoverable HMIStewart Smith1-0/+3
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> [stewart@linux.vnet.ibm.com: unlock before return (suggested by Mahesh/Andrew), disable only on non-cancelling fsp codeupdate call (suggested by Vasant)] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-10-24pci: Remove obsoleted PCI slot pfreset() operationGavin Shan4-39/+30
PCI slot pfreset() operation is obsoleted as nobody uses it. This removes it and the related PCI slot states. No functional changes introduced. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Acked-by: Russell Currey <ruscur@russell.cc> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-10-17hw/phb3: Override root slot's prepare_link_change() with PHB'sGavin Shan1-0/+8
For PCI slot behind root port, its prepare_link_change() should be same to PHB's. Otherwise, the UTL events cannot be masked when the slot is reseted, leading to EEH error because of UTL link-down event. Cc: stable # 5.3.0+ Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-10-17hw/phb3: Disable surprise link down event on PCI slotsGavin Shan1-8/+49
This masks surprise link down event on RC or downtream ports if the PCI slots behind them support PCI surprise hotplug. The event should be handled by PCI hotplug driver instead of EEH subsystem. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>