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2021-08-06xive/p10: Add a XIVE2 driverCédric Le Goater1-2/+4
The XIVE2 interrupt controller of the POWER10 processor follows the same logic than on POWER9 but the HW interface has been largely reviewed. It has a new register interface, different BARs, extra VSDs, new layout for the XIVE structures, and a set of new features which are described below. The OPAL XIVE2 driver code activating this controller was duplicated from P9 for clarity as the registers and structures have changed considerably. The same OPAL interface is implemented for OS compatibility and it should not impact existing Linux kernels, KVM included. Guest OS is not impacted either. Support for new features will be implemented in time and will require new support from the OS. * XIVE2 BARS The interrupt controller BARs have a different layout outlined below. Each sub-engine has now own its range and the indirect TIMA access was replaced with a set of pages, one per CPU, under the IC BAR: - IC BAR (Interrupt Controller) . 4 pages, one per sub-engine . 128 indirect TIMA pages - TM BAR (Thread Interrupt Management Area) . 4 pages - ESB BAR (ESB pages for IPIs) . up to 1TB - END BAR (ESB pages for ENDs) . up to 2TB - NVC BAR (Notification Virtual Crowd) . up to 128 - NVPG BAR (Notification Virtual Process and Group) . up to 1TB - Direct mapped Thread Context Area (reads & writes) OPAL does not use the grouping and crowd capability. * Virtual Structure Tables XIVE2 adds new tables types and also changes the field layout of the END and NVP Virtualization Structure Descriptors. - EAS - END new layout - NVT was splitted in : . NVP (Processor), 32B . NVG (Group), 32B . NVC (Crowd == P9 block group) 32B - IC for remote configuration - SYNC for cache injection - ERQ for event input queue The setup is slighly different on XIVE2 because the indexing has changed for some of the tables, block ID or the chip topology ID can be used. * XIVE2 features SCOM and MMIO registers have a new layout and XIVE2 adds a new global capability and configuration registers. The lowlevel hardware offers a set of new features among which : - cache injection mechanism - 4 cache watch engines - a configurable number of priorities : 1 -8 - StoreEOI with load-after-store ordering is activated by default - new sync/kill operations for cache operations Other features will have some impact on the Hypervisor and guest OS when activated, but this is not required for initial support of the controller. - Gen2 TIMA layout - A P9-compat mode, or Gen1, TIMA toggle bit for SW compatibility - Automatic Context save & restore - increase to 24bit for VP number - New escalations schems : ESB, Adaptive, CPPR POWER10 adds support for User interrupts. When configured, the XIVE2 controller can notify directly user processes using the Event Based Branch exception line of the thread. If not running, the OS is notified through an escalation event. New OPAL and PAPR interfaces will be required and OS support needs to be studied. * XIVE2 P9-compat mode, or Gen1 The thread interrupt management area (TIMA) is a set of pages mapped in the Hypervisor and in the guest OS address space giving access to the interrupt thread context registers for interrupt management, ACK, EOI, CPPR, etc. XIVE2 changes slightly the TIMA layout with extra bits for the new features, larger CAM lines and the controller provides configuration switches for backward compatibility. This is called the XIVE2 P9-compat mode, of Gen1 TIMA. It impacts the layout of the TIMA and the availability of the internal features associated with it, Automatic Save & Restore for instance. Using a P9 layout also means setting the controller in such a mode at init time. The XIVE2 driver in OPAL chooses to initialize the XIVE2 controller with a XIVE2/P10 TIMA directly because the layouts are compatible with the Linux PowerNV and the guest OSes expectations. For KVM support, the OPAL calls abstract the HW interface and no assumption is made on the OS CAM line width. * Activating new XIVE2 features Everything related to OPAL internals such as the use of the new cache sync mechanism can be implemented in time without impact on the OS. Other features will require new device tree properties exposed to the OS and extra support for the OS. Automatic Context save & restore is one of the first feature which should be looked at. * XICS-over-XICS driver (P8 compatibility) The P8 emulation mode is an OPAL compat interface used for Linux kernels which did not have XIVE native support. This was useful for POWER9 bringup but it is much less now. As it was adding a lot of complexity and reducing the interrupt controller resources, this mode is not available in the XIVE2 driver for POWER10. It will still be possible to add this compat mode in the future if required. The OS will have to reset the driver at boot time, like on POWER9. * Impact on other drivers (PSI, PHB, NPU) Interrupts are allocated in a very similar way. Each controller might have different ESB characteristics, StoreEOI support, 64K pages for PSI. All is in place to support these changes already. PHB5 will have support for "address-based trigger mode", probably in the DD2.0 time frame when verification is completed. When activated, the XIVE IC ESB pages will be used instead of the PHB ESB pages for a lower interrupt latency. LSI will still use old fashion triggers without StoreEOI. * Yet to be addressed : - OPAL P10 interface incomplete (stop states) - Clarify the PHB5 strategy regarding the use of the XIVE IC ESB pages instead of the PHB ones when address-based trigger mode is supported. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2020-12-15xive/p9: Remove assert from xive_eq_for_target()Cédric Le Goater1-1/+1
XIVE VPs are structures describing the vCPUs of guests. When starting a guest, these are allocated and enabled and some checks are done on the location of the associated ENDs, which describe the event queues. If the block of the VP and the block of the ENDs do not match, the XIVE driver asserts. Unfortunately, there is no way to check that a VP identifier is part of a VP block that was previously allocated and it is relatively easy to crash the host with a bogus VP id. That can be done with a QEMU hack on a machine using vsmt. Simply remove the assert, the OS should gracefully handle the error. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reported-by: Greg Kurz <groug@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2020-11-27xive/p9: Add a retry counter when updating the cache watchCédric Le Goater1-1/+9
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2020-11-27xive/p9: Introduce XIVE_ESB_PAGE_SIZECédric Le Goater1-8/+8
Rename XIVE_ESB_SIZE to XIVE_ESB_PAGE_SIZE in the xive/p9 driver to be consistent with the xive2/p10 driver. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2020-11-27xive/p9: Use local_alloc() to allocate the XIVE bitmapsCédric Le Goater1-3/+7
These bitmaps are big (128K). On systems with multiple sockets, we will run out of heap. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2020-08-07xive: Set the fused core mode properlyBenjamin Herrenschmidt1-0/+4
Set or clear the fused core mode bit in the XIVE inits properly. While HostBoot is supposed to do it, I prefer not depending on it doing the right thing, since we already configure that register ourselves anyway. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-08-07Add basic P9 fused core supportRyan Grimm1-1/+1
P9 cores can be configured into fused core mode where two core chiplets function as an 8-threaded, single core. So, bump four to eight in boot_entry when in fused core mode and cpu_thread_count in init_boot_cpu. The HID, AMOR, TSCR, RPR require the first active thread on that core chiplet to load the copy for that core chiplet. So, send thread 1 of a fused core to init_shared_sprs in boot_entry. The code checks for fused core mode in the core thead state register and puts a field in struct cpu_thread. This flag is checked when updating the HID and in XIVE code when setting the special bar. For XSCOM, the core ID is the non-fused EX. So, create macros to arrange the bits. It's fairly verbose but somewhat readable. This was tested on a P9 ZZ with 16 fused cores and ran HTX for over 24 hours. Signed-off-by: Ryan Grimm <grimm@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-08-07xive/p9: Enforce thread enablement before TIMA accessesCédric Le Goater1-0/+15
To activate the HW thread context ring, and its associated thread interrupt registers, a thread needs to raise the VT bit in word2. This requires access to the TIMA and this access is only granted if the thread was first enabled at the XIVE IC level. This is done in a sequence in xive_cpu_callin() but there is a chance that the accesses done on the TIMA do not see the update of the enable register. To make sure that the enablement has completed, add an extra load on the PC_THREAD_EN_REGx register. This guarantees that the TIMA accesses will see the latest state of the enable register. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-08-07xive: Fix typos in commentsGustavo Romero1-2/+2
Fix a typo in comment about Presentation Controller Base Address Register and another typo about code to configure the queue overflows. Signed-off-by: Gustavo Romero <gromero@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive: Fix two typos in commentsGustavo Romero1-2/+2
This commit fixes two typos in XIVE comments about how to handle an escalation event. Signed-off-by: Gustavo Romero <gromero@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/P9: Use NUM_INT_PRIORITIES in xive_reset()Cédric Le Goater1-1/+1
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Introduce XIVE_ESB_SIZECédric Le Goater1-7/+8
Replace 0x20000 with a clear define. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: use PAGE_SIZECédric Le Goater1-19/+19
Signed-off-by: Cédric Le Goater <clg@kaod.org> [oliver: added prev patch, minor style fix] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30hw/xive: Use XIVE_VSD_SIZE moreOliver O'Halloran1-2/+2
I think Cedric forgot this patch at some point. Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Introduce definitions for VP ids of HW threadsCédric Le Goater1-13/+22
The CAM line of the HW context is 23bits wide and its value is hardcoded in the XIVE IC presenter with : |chip|000000000001|thrdid | To make sure that we won't assign a VP id overlapping with the HW CAM line, we reserve range 0x80..0xff in our VP allocator. Make that clear. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Modify the size of the VP spaceCédric Le Goater1-8/+12
The VP space is 19bits wide but the number of XIVE VPs software can use depends on the configured number of EQs. We have 1M EQs and we use 8 priorities per VP. Therefore, our VP space is limited to 128k. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Force 64K page size on the IC and TM BARsCédric Le Goater1-21/+6
It is possible to configure the IC and TM BAR mappings using 4k pages but we never do. Remove the code doing so. Reviewed-by: Gustavo Romero <gromero@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Clarify indirect table allocationCédric Le Goater1-12/+17
The XIVE interrupt controller uses a set of Virtualization Structure Tables (VST) which characteristics, type, address, size, are described by Virtual Structure Descriptors (VSD). A VSD is 64bit wide. The EQ and VP tables are indirect tables. The VSD points to a single page of VSDs each pointing to a page of virtual structures. Indirect tables are limited to a single top page which is enough to cover the whole range of EQs (24 bits) and VPs (19bits). Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Use sizeof() instead of hardcoded valuesCédric Le Goater1-2/+3
Reviewed-by: Gustavo Romero <gromero@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Introduce XIVE_EQ_SHIFTCédric Le Goater1-2/+3
Each EQ descriptor is associated with a pair of ESB pages. The even page controls the ESn PQ bits and the odd page controls the ESe PQ bits. Reviewed-by: Gustavo Romero <gromero@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Clarify the escalation IRQ encodingCédric Le Goater1-4/+9
When an interrupt can not be delivered, an escalation interrupt can be triggered. The EQ descriptor of the pending interrupt should be configured to generate an escalation event, using the EQ_W0_ESCALATE_CTL 'e' bit, and words 4 and 5 of the EQ descriptor should contain an IVE pointing to the escalation EQ to trigger. This is why EQ descriptors are considered as interrupt sources and registered as such when initializing the interrupt controller. These interrupts are identified as escalations by the OPAL XIVE interface, OPAL calls and internal routines, by setting a special bit in their global interrupt number. Clarify that and check that the number of EQ descriptors is not overflowing the global interrupt encoding. Reviewed-by: Gustavo Romero <gromero@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Introduce XIVE_EQ_ORDERCédric Le Goater1-8/+9
XIVE_EQ_ORDER defines the number of EQ descriptors per chip the system can use. The EQ descriptors can be controlled by ESB pages also and the driver defines in the VC BAR of the controller a range of 128G of ESB pages giving access to 1M EQs. All ESB pages are backed by a memory table, so we are fine but we could improve the configuration. Reviewed-by: Gustavo Romero <gromero@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Introduce XIVE_ESB_SHIFTCédric Le Goater1-4/+6
Each interrupt source is associated with a pair of ESB pages. The even page is for trigger and the odd page is for management. Reviewed-by: Gustavo Romero <gromero@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Clarify the global IRQ number encodingCédric Le Goater1-6/+13
On P9, the global IRQ number is limited to 24 bits because the XICS emulation encodes the CPPR value in the top 8 bits. The following 4 bits are used to encode the XIVE block number, which leaves 20 bits for the interrupt index number. Introduce a definition reflecting the size of this bitfield and check that number of interrupts per chip is not overflowing our encoding. Reviewed-by: Gustavo Romero <gromero@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-30xive/p9: Introduce XIVE_INT_ORDERCédric Le Goater1-14/+20
The size of the interrupt number space is constrained by the block and index fields of the trigger data exchanged between source units and the XIVE IC. These are respectively 4 and 28 bits, which gives us a 32 bits interrupt number space. But the XICS emulation requires 8 bits to encode the CPPR value. The system interrupt number space is therefore constrained to 24 bits and on a chip, to 20 bits because the XIVE driver configures the HW to use one block per chip. XIVE_INT_ORDER defines the size of the interrupt number space : 1M per chip. To control these interrupts, the driver defines in the VC BAR of the controller a range of 384G of ESB pages giving access to 3M interrupts. The VSD for the memory table is smaller than the index and accesses to some ESB pages are not backed by a memory table structure. If such an access occurred, it would result in a FIR. It never happened but this is something to fix with a finer configuration of the VC BAR. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-06-03xive: Fix typo and spelling in a commentGustavo Romero1-1/+1
This commit fixes a typo and a spelling in a comment about the XIVE set translate mechanism. Signed-off-by: Gustavo Romero <gromero@linux.ibm.com> Reviewed-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-03-12Re-license IBM written files as Apache 2.0 OR GPLv2+Stewart Smith1-1/+1
SPDX makes it a simpler diff. I have audited the commit history of each file to ensure that they are exclusively authored by IBM and thus we have the right to relicense. The motivation behind this is twofold: 1) We want to enable experiments with coreboot, which is GPLv2 licensed 2) An upcoming firmware component wants to incorporate code from skiboot and code from the Linux kernel, which is GPLv2 licensed. I have gone through the IBM internal way of gaining approval for this. The following files are not exclusively authored by IBM, so are *not* included in this update (I will be seeking approval from contributors): core/direct-controls.c core/flash.c core/pcie-slot.c external/common/arch_flash_unknown.c external/common/rules.mk external/gard/Makefile external/gard/rules.mk external/opal-prd/Makefile external/pflash/Makefile external/xscom-utils/Makefile hdata/vpd.c hw/dts.c hw/ipmi/ipmi-watchdog.c hw/phb4.c include/cpu.h include/phb4.h include/platform.h libflash/libffs.c libstb/mbedtls/sha512.c libstb/mbedtls/sha512.h platforms/astbmc/barreleye.c platforms/astbmc/garrison.c platforms/astbmc/mihawk.c platforms/astbmc/nicole.c platforms/astbmc/p8dnu.c platforms/astbmc/p8dtu.c platforms/astbmc/p9dsu.c platforms/astbmc/vesnin.c platforms/rhesus/ec/config.h platforms/rhesus/ec/gpio.h platforms/rhesus/gpio.c platforms/rhesus/rhesus.c platforms/astbmc/talos.c platforms/astbmc/romulus.c Signed-off-by: Stewart Smith <stewart@linux.ibm.com> [oliver: fixed up the drift] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-16xive: make endian-cleanNicholas Piggin1-185/+204
Convert xive opal calls, dt construction, and in-memory hardware tables to use explicit endian conversions. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-11xive/p9: sbe size debug print fixNicholas Piggin1-1/+1
Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-11xive/p9: use predefined bitmasks to manipulate EQ addressesNicholas Piggin1-2/+3
This catches one more case missed by commit 2354857fca. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-11xive/p9: improve cache watch type checkingNicholas Piggin1-46/+40
The cache update functions take void * pointer with sizing information in order to operate on some fundamentally different types. Make specific functions for each type, which use proper types. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: introduce the ESB magic MMIO offsetsCédric Le Goater1-10/+10
The following offsets into the ESB MMIO allow to read or manipulate the PQ bits. They must be used with an 8-byte load instruction. They all return the previous state of the interrupt (atomically). Additionally, some ESB pages support doing an EOI via a store and some ESBs support doing a trigger via a separate trigger page. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: use predefined bitmasks to manipulate EQ addressesCédric Le Goater1-3/+3
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: remove XIVE_INT_SAFETY_GAPCédric Le Goater1-5/+9
It was used by bringup code only. Using HW interrupt numbers in a high range was a way to check that HW interrupt numbers (OPAL) and logical interrupt numbers (Linux) were not getting mixed in the event queues. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: introduce NVT_SHIFTCédric Le Goater1-2/+5
This defines the size of our VP space which is constrained by the definition of the END structure in the XIVE architecture for POWER9: #define EQ_W6_NVT_BLOCK PPC_BITMASK32(9,12) #define EQ_W6_NVT_INDEX PPC_BITMASK32(13,31) The NVT/VP id is returned to the hypervisor by the OPAL call opal_xive_get_vp_info() and later pushed in W2 of the OS CAM line when a vCPU is dispatched on an HW thread. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: remove ACK# setting in the NVTCédric Le Goater1-1/+0
The pressure relief is disabled (PC_TCTXT_CFG_STORE_ACK) because we use the same field in the NVT W1 to stash the VP END base index. We do not need to disable manually the ACK# register in the NVT W5. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: cleanup all EQs when a VP block is freed.Cédric Le Goater1-1/+1
EQ 7 was missing from the cleanup loop. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: fix silent escalation EQ setupCédric Le Goater1-1/+3
When setting the silent/gather escalation for a VP, all EQs [0-6] should point to the silent EQ 7. Fix the loop in routine xive_setup_silent_gather() to include EQ 6 which was missing. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: introduce definitions for prioritiesCédric Le Goater1-8/+16
The priority number 7 is used in a couple of places but it has different meanings. It can be the maximum priority number or the escalation priority number. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: fix EQ bitmap assignment when allocation failsCédric Le Goater1-6/+7
Wehn allocating a EQ set for a VP, the EQ base index bit is marked as allocated even if allocation fails, due to a lack of available pages. Move bit assignment at the end of xive_alloc_eq_set(). Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: obsolete OPAL_XIVE_IRQ_SHIFT_BUG flagsCédric Le Goater1-7/+0
These were needed to workaround HW bugs in PHB4 LSIs of POWER9 DD1.0 processors. HW395455 P9/PHB4: Wrong Interrupt ESB CI Load Opcode Location in 64K page mode Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: obsolete OPAL_XIVE_IRQ_*_VIA_FW flagsCédric Le Goater1-12/+0
These were needed to workaround HW bugs in PHB4 LSIs of POWER9 DD1.0 processors. Keep the flags in case of a similar issue in the next generation of the XIVE logic and keep it also for Linux which still has handlers in its XIVE layer. However, there is no need to keep the code in POWER9 XIVE driver. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: remove dead codeCédric Le Goater1-4/+0
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: remove code not using block group modeCédric Le Goater1-208/+1
block group mode is now required, it can not be disabled. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: remove code not using indirect modeCédric Le Goater1-111/+12
An indirect table is a one page array of XIVE VSDs pointing to subpages containing XIVE virtual structures: NVTs, ENDs, EASs or ESBs. The OPAL XIVE driver uses direct tables for the EAS and ESB tables. The number of interrupts being 1M, the tables are respectivelly 256K and 8M per chip. We want the EAS lookup to be fast so we keep this table direct. The NVT and END are bigger structures (64 and 32 bytes). If the table were direct, we would use 32M and 32M of OPAL memory per chip. They are indirect today and Linux allocates the pages on behalf of OPAL when a new indirect subpage is needed. We plan to increase the NVT space and END space in P10. Remove USE_INDIRECT ifdef and associated code not used anymore. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: use MMIO access for VC_EQC_CONFIGCédric Le Goater1-1/+1
There is no reason to issue loads on XSCOM when syncing the interrupt controller. All should be in place to use MMIOs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: minor cleanup of the interfaceCédric Le Goater1-2/+2
The XIVE driver exposes an API to the core OPAL layer and to other OPAL drivers. This is a minor cleanup preparing ground for future XIVE logic. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-04xive/p9: introduce header files for the registersCédric Le Goater1-2/+4
This is moving the definitions of the registers of the P9 XIVE interrupt controller and the P9 XIVE internal structures in a specific header file and moving the definitions related to the thread interrupt context area to a common file. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-09-06hw/psi-p9: Mask OPAL-owned LSIs without handlersOliver O'Halloran1-0/+7
Some versions of Swift have the TPM interrupt line of the second chip pulled up instead of down. This causes the PSI's external (TPM) interrupt to constantly re-fire since it's an LSI and the interrupt signal is constantly active. There's nothing that can be done to clear the underlying interrupt condition so we to ensure that it's masked. The problem isn't really specific to the external interrupt and will occur for any of the PSI interrupts that don't have an actual handler (FSP, global error, and sometimes the external). When one of these is delivered to OPAL we should log that it happened and mask it to prevent re-firing. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-09-06xive: fix return value of opal_xive_allocate_irq()Cédric Le Goater1-1/+1
When the maximum number of interrupts per chip is reached, xive_try_allocate_irq() returns an internal XIVE error: XIVE_ALLOC_NO_SPACE. But its value 0xffffffff is interpreted as a positive value by its caller opal_xive_allocate_irq() and not as an error. opal_xive_allocate_irq() returns this value to Linux which also considers 0xffffffff as a valid interrupt number and tries to get the interrupt characteritics using opal_xive_get_irq_info(). This OPAL calls finally fails leading to all sort of errors on the host which is not prepared for such a scenario. Code impacted are the IPI setup and the both XIVE KVM devices. Fix by returning OPAL_RESOURCE from xive_try_allocate_irq() which is consistent with the other errors returned by this routine. This fixes the behavior in opal_xive_allocate_irq() and in Linux. A workaround could be introduced in Linux to consider 0xffffffff as a OPAL_RESOURCE value. This assumption is valid with the current XIVE IRQ number encoding. Fixes: 07946e68f47a ("xive: Add interrupt allocator") Reported-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> [oliver: Added fixes tag] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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