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2018-08-02xive: Disable block trackerBenjamin Herrenschmidt1-2/+4
Due to some HW errata, the block tracking facility (performance optimisation for large systems) should be disabled on Nimbus chips. Disable it unconditionally for now. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-05-01SLW: quieten 'Configuring self-restore' for DARN,NCU_SPEC_BAR and HRMORStewart Smith1-1/+1
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-04-29xive: fix missing unlock in error pathStewart Smith1-0/+1
Found with sparse and some added lock annotations. CC: stable # 5.10+ Fixes: de82c2e0e Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-04-03xive: disable store EOI supportCédric Le Goater1-3/+10
Hardware has limitations which would require to put a sync after each store EOI to make sure the MMIO operations that change the ESB state are ordered. This is a killer for performance and the PHBs do not support the sync. So remove the store EOI for the moment, until hardware is improved. Also, while we are at changing the XIVE source flags, let's fix the settings for the PHB4s which should follow these rules : - SHIFT_BUG for DD10 - STORE_EOI for DD20 and if enabled - TRIGGER_PAGE for DDx0 and if not STORE_EOI Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-03-22xive: fix opal_xive_set_vp_info() error pathCédric Le Goater1-1/+1
In case of error, opal_xive_set_vp_info() will return without unlocking the xive object. This is most certainly a typo. Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-30xive: Mask MMIO load/store to bad location FIRFrederic Barrat1-1/+7
For opencapi, the trigger page of an interrupt is mapped to user space. The intent is to write the page to raise an interrupt but there's nothing to prevent a user process from reading it, which has the infortunate consequence of checkstopping the system. Mask the FIR bit raised when an MMIO operation targets an invalid location. It's the recommendation from recent documentation and hostboot is expected to mask it at some point. In the meantime, let's play it safe. Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14SCOM restore for DARN and XIVEAkshay Adiga1-0/+30
While waking up from stop11, we want NCU_DARN_BAR to have enable bit set. Without this stop_api call, the value restored is without enable bit set. We loose NCU_SPEC_BAR when the quad goes into stop11, stop_api will restore while waking up from stop11. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-11xive: Ensure VC informational FIRs are maskedBenjamin Herrenschmidt1-0/+5
Some HostBoot versions leave those as checkstop, they are harmless and can sometimes occur during normal operations. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Tested-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-11xive: Fix occasional VC checkstops in xive_resetBenjamin Herrenschmidt1-3/+54
The current workaround for the scrub bug described in __xive_cache_scrub() has an issue in that it can leave dirty invalid entries in the cache. When cleaning up EQs or VPs during reset, if we then remove the underlying indirect page for these entries, the XIVE will checkstop when trying to flush them out of the cache. This replaces the existing workaround with a new pair of workarounds for VPs and EQs: - The VP one does the dummy watch on another entry than the one we scrubbed (which does the job of pushing old stores out) using an entry that is known to be backed by a permanent indirect page. - The EQ one switches to a more efficient workaround which consists of doing a non-side-effect ESB load from the EQ's ESe control bits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-11xive: Do not return a trigger page for an escalation interruptBenjamin Herrenschmidt1-2/+2
This is bogus, we don't support them. (Thankfully the callers didn't actually try to use this on escalation interrupts). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Tested-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-11xive: Mark a freed IRQ's IVE as valid and maskedBenjamin Herrenschmidt1-1/+1
Removing the valid bit means a FIR will trip if it's accessed inadvertently. Under some circumstances, the XIVE will speculatively access an IVE for a masked interrupt and trip it. So make sure that freed entries are still marked valid (but masked). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Tested-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-03direct-controls: enable fast reboot direct controls for mamboNicholas Piggin1-1/+6
Add mambo direct controls to stop threads, which is required for reliable fast-reboot. Enable direct controls by default on mambo. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-03fast-reboot: bare bones fast reboot implementation for POWER9Nicholas Piggin1-5/+27
This is an initial fast reboot implementation for p9 which has only been tested on the Witherspoon platform, and without the use of NPUs, NX/VAS, etc. This has worked reasonably well so far, with no failures in about 100 reboots. It is hidden behind the traditional fast-reboot experimental nvram option, until more platforms and configurations are tested. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-28xive: Remove obsolete commentBenjamin Herrenschmidt1-2/+0
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-28xive: Don't bother cleaning up disabled EQs in resetBenjamin Herrenschmidt1-4/+9
Additionally, warn if we find an enabled one that isn't one of the firmware built-in queues. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-28xive: Warn on valid VPs found in abnormal casesBenjamin Herrenschmidt1-1/+4
If an allocated VP is left valid at xive_reset() or Linux tries to free a valid (enabled) VP block, print errors. The former happens occasionally if kdump'ing while KVM is running so keep it as a debug message. The latter is a programming error in Linux so use a an error log level. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-28xive: Properly reserve built-in VPs in non-group modeBenjamin Herrenschmidt1-0/+2
This is not normally used but if the #define is changed to disable block group mode we would incorrectly clear the buddy completely without marking the built-in VPs reserved. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-28xive: Quieten debug messages in standard buildsBenjamin Herrenschmidt1-18/+18
This makes a bunch of messages, especially the per-cpu ones, only enabled in debug builds. This avoids clogging up the OPAL logs with XIVE related messages that have proven not being particularily useful for field defects. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-28xive: Implement "single escalation" featureBenjamin Herrenschmidt1-13/+178
This adds a new VP flag to control the new DD2.0 "single escalation" feature. This feature allows us to have a single escalation interrupt per VP instead of one per queue. It works by hijacking queue 7 (which is this no longer usable when that is enabled) and exploiting two new hardware bits that will: - Make the normal queues (0..6) escalate unconditionally thus ignoring the ESe bits. - Route the above escalations to queue 7 - Have queue 7 silently escalate without notification Thus the escalation of queue 7 becomes the one escalation interrupt for all the other queues. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-28xive: When disabling a VP, wipe all of its settingsBenjamin Herrenschmidt1-5/+5
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-28xive: Improve cleaning up of EQsBenjamin Herrenschmidt1-11/+34
Factors out the function that sets an EQ back to a clean state and add a cleaning pass for queue left enabled when freeing a block of VPs. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-28xive: When disabling an EQ, wipe all of its settingsBenjamin Herrenschmidt1-50/+51
This avoids having configuration bits left over Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-09xive: Trivial fix for compilation error when enabling xive debugGuilherme G. Piccoli1-1/+1
Without this, we get: hw/xive.c: In function ‘xive_special_cache_check’: hw/xive.c:2982:9: error: missing initializer for field ‘w0’ of ‘struct xive_vp’ [-Werror=missing-field-initializers] Signed-off-by: Guilherme G. Piccoli <gpiccoli@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-09xive: Fix ability to clear some EQ flagsBenjamin Herrenschmidt1-0/+4
We could never clear "unconditional notify" and "escalate" Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-09xive: Update inits for DD2.0Benjamin Herrenschmidt1-2/+27
This updates some inits based on information from the HW designers. This includes enabling some new DD2.0 features that we don't yet exploit. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-15xive: Fix VP free block group mode false-positive parameter checkNicholas Piggin1-1/+3
The check to ensure the buddy allocation idx is aligned to its allocation order was not taking into account the allocation split. This would result in opal_xive_free_vp_block failures despite giving the same value as returned by opal_xive_alloc_vp_block. E.g., starting then stopping 4 KVM guests gives the following pattern in the host: opal_xive_alloc_vp_block(5)=0x45000020 opal_xive_alloc_vp_block(5)=0x45000040 opal_xive_alloc_vp_block(5)=0x45000060 opal_xive_alloc_vp_block(5)=0x45000080 opal_xive_free_vp_block(0x45000020)=-1 opal_xive_free_vp_block(0x45000040)=0 opal_xive_free_vp_block(0x45000060)=-1 opal_xive_free_vp_block(0x45000080)=0 Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Fix opal_xive_dump_tm() to access W2 properlyBenjamin Herrenschmidt1-1/+7
The HW only supported limited access sizes. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Make opal_xive_allocate_irq() properly try all chipsBenjamin Herrenschmidt1-17/+37
When requested via OPAL_XIVE_ANY_CHIP, we need to try all chips. We first try the current one (on which the caller sits) and if that fails, we iterate all chips until the allocation succeeds. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Fix initialization & cleanup of HW thread contextsBenjamin Herrenschmidt1-36/+38
Instead of trying to "pull" everything and clear VT (which didn't work and caused some FIRs to be set), instead just clear and then set the PTER thread enable bit. This has the side effect of completely resetting the corresponding thread context. This fixes the spurrious XIVE FIRs reported by PRD and fircheck Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Add debug option for detecting misrouted IPI in emulationBenjamin Herrenschmidt1-15/+116
This is high overhead so we don't enable it by default even in debug builds, it's also a bit messy, but it allowed me to detect and debug a locking issue earlier so it can be useful. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Increase the interrupt "gap" on debug buildsBenjamin Herrenschmidt1-2/+7
We normally allocate IPIs from 0x10. Make that 0x1000 on debug builds to limit the chances of overlapping with Linux interrupt numbers which makes debugging code that confuses them easier. Also add a warning in emulation if we get an interrupt in the queue whose number is below the gap. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Fix locking around cache scrub & watchBenjamin Herrenschmidt1-0/+19
Thankfully the missing locking only affects debug code and init code that doesn't run concurrently. Also adds a DEBUG option that checks the lock is properly held. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Use symbolic constantBenjamin Herrenschmidt1-1/+1
Cosmetic fix. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Workaround HW issue with scrub facilityBenjamin Herrenschmidt1-1/+32
Without this, we sometimes don't observe from a CPU the values written to the ENDs or NVTs via the cache watch. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Add exerciser for cache watch/scrub facility in DEBUG buildsBenjamin Herrenschmidt1-45/+96
This runs 1000 iterations exercising the cache watch and scrub facilities on VPs and ENDs at boot. This exposes a HW bug with the scrub which will be worked around in a subsequent patch. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Make assertion in xive_eq_for_target() more informativeBenjamin Herrenschmidt1-1/+5
If this fails, print a bit more info about it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Add debug code to check initial cache updatesBenjamin Herrenschmidt1-0/+47
This adds debug code to check that the initial updates of in-memory VPs and EQs via the cache watch and cache scrub facilities has worked properly. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Ensure pressure relief interrupts are disabledBenjamin Herrenschmidt1-0/+2
We don't use them and we hijack the VP field with their configuration to store the EQ reference, so make sure the kernel or guest can't turn them back on by doing MMIO writes to ACK# Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Don't try setting the reserved ACK# field in VPsBenjamin Herrenschmidt1-4/+1
That doesn't work, the HW doesn't implement it in the cache watch facility anyway. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12xive: Remove useless memory barriers in VP/EQ initsBenjamin Herrenschmidt1-2/+0
We no longer update "live" memory structures, we use a temporary copy on the stack and update the actual memory structure using the cache watch, so those barriers are pointless. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-15hw/xive: Fix unchecked return value in opal_xive_dump_emu() (CID 144257)Cyril Bur1-4/+9
This is a function to display information, if xive_get_irq_targetting() fails then the target printed would be the initial value of 0xFF. It costs nothing to check the return value and print very obviously question marks. Fixes: CID 144257 Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-15hw/xive: Check return value from xive_decode_vp() (CID 142343 142344)Cyril Bur1-2/+8
While it is likely that a failure of xive_decode_vp() would simply trip an error condition later on, it makes sense to check for errors earlier and print a (hopefully) more relevant error message. Fixes: CID 142343 and 142344 Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-15hw/xive: Fix NULL return value dereferences (CID 141079 & 141081)Cyril Bur1-1/+5
Add NULL checks, it is highly likely that these situations are 'impossible', these checks only serve to be extra safe. Fixes: CID 141079 and 141081 Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-11xive: Check for valid PIR index when decodingRussell Currey1-0/+4
This fixes an unlikely but possible assert() fail on kdump. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Russell Currey <ruscur@russell.cc> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-12xive: Enable memory backing of queuesBenjamin Herrenschmidt1-6/+35
This dedicates 6x64k pages of memory permanently for the XIVE to use for internal queue overflow. This allows the XIVE to deal with some corner cases where the internal queues might prove insufficient. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-12xive: Properly get rid of donated indirect pages during resetBenjamin Herrenschmidt1-38/+98
Otherwise they keep being used accross kexec causing memory corruption in subsequent kernels once KVM has been used. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26xive: Remove historical BAR reading codeBenjamin Herrenschmidt1-80/+11
We always use physmap to assign them, take out the code that tries to read and check the validity of the setup done by HB or cronus. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26xive: DD2.0 updatesBenjamin Herrenschmidt1-8/+48
Add support for StoreEOI, fix StoreEOI MMIO offset in ESB page, and other cleanups Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-21xive: Fix initialisation of xive_cpu_state structAndrew Donnellan1-0/+1
When using XIVE emulation with DEBUG=1, we run into crashes in log_add() due to the xive_cpu_state->log_pos being uninitialised (and thus, with DEBUG enabled, initialised to the poison value of 0x99999999). Zero out the xive_cpu_state to fix this. Fixes: 6480d9656348 ("XIVE: Base XIVE support for OPAL XICS emulation calls") Reported-by: Alastair D'Silva <alastair@d-silva.org> Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-16hw/phys_map: Use GCIDs as a chip indexOliver O'Halloran1-7/+5
Currently we pass in a proc_chip structure to phys_map_get(). All we we really need from this structure is the Global Chip ID (GCID). This patch reworks the function so that we only need to pass the GCID which allows us to use it before the proc_chip structures have been initialised (i.e in the HDAT parser). Cc: Michael Neuling <mikey@neuling.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Acked-By: Michael Neuling <mikey@neuling.org> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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