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2019-12-05hw/port80: Squash No SYNC errorOliver O'Halloran1-1/+6
[ Upstream commit 6cf9ace9d69dcb5c37b328625132bc5c9624b778 ] On Aspeed BMCs can be configured to route LPC IO address 0x80 to a GPIO port. Some systems use this to implement a boot progress indicator, but not all of them. There's no easy way to tell if this has been setup or not and if it hasn't we get an LPC SYNC no-response error from out LPC master. When we reach Linux and enable interrupts this results in this spurious error being printed: LPC[000]: Got SYNC no-response error. Error address reg: 0xd0010082 lpc_probe_write() is intended to catch situations where the peripherial being written to might not be configured, so use that instead of lpc_outb() to squash the error. Cc: Ranga <stewart@flamingspork.com> Cc: Andrew Jeffery <andrew@aj.id.au> Acked-by: Andrew Jeffery <andrew@aj.id.au> [oliver: fixed the test] Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2019-07-26hw/phys-map: Add Axone memory mapReza Arbab1-0/+1
Add the physical memory map for Axone systems. According to 'make hw-check', there are no holes or overlapping regions. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Acked-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Acked-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26hw/phys-map: Add pvr argument to phys_map_init()Reza Arbab1-4/+12
When new chip types are added, phys_map_init() will need to know which memory map it should use. Instead of directly checking PVR, make it an argument to the function, so that 'make hw-check' can test all the maps. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Acked-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Acked-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26SPDX-ify all skiboot codeStewart Smith2-26/+8
Use Software Package Data Exchange (SPDX) to indicate license for each file that is unique to skiboot. At the same time, ensure the (C) who and years are correct. See https://spdx.org/ Signed-off-by: Stewart Smith <stewart@linux.ibm.com> [oliver: Added a few missing files] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-06-03lpc-port80h: Don't write port 80h when running under SimicsAlistair Popple1-0/+2
Simics doesn't model LPC port 80h. Writing to it terminates the simulation due to an invalid LPC memory access. This patch adds a check to ensure port 80h isn't accessed if we are running under Simics. Signed-off-by: Alistair Popple <alistair@popple.id.au> [stewart: fixup run-port80h test] Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-05-02Write boot progress to LPC ports 81 and 82Stewart Smith1-2/+24
There's a thought to write more extensive boot progress codes to LPC ports 81 and 82 to supplement/replace any reliance on port 80. We want to still emit port 80 for platforms like Zaius and Barreleye that have the physical display. Ports 81 and 82 can be monitored by a BMC though. Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-05-02Write boot progress to LPC port 80hStewart Smith2-1/+91
This is an adaptation of what we currently do for op_display() on FSP machines, inventing an encoding for what we can write into the single byte at LPC port 80h. Port 80h is often used on x86 systems to indicate boot progress/status and dates back a decent amount of time. Since a byte isn't exactly very expressive for everything that can go on (and wrong) during boot, it's all about compromise. Some systems (such as Zaius/Barreleye G2) have a physical dual 7 segment display that display these codes. So far, this has only been driven by hostboot (see hostboot commit 90ec2e65314c). Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-02-19hw/test: generalise makefileStewart Smith1-9/+9
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2017-06-16hw/phys_map: Use GCIDs as a chip indexOliver O'Halloran1-5/+5
Currently we pass in a proc_chip structure to phys_map_get(). All we we really need from this structure is the Global Chip ID (GCID). This patch reworks the function so that we only need to pass the GCID which allows us to use it before the proc_chip structures have been initialised (i.e in the HDAT parser). Cc: Michael Neuling <mikey@neuling.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Acked-By: Michael Neuling <mikey@neuling.org> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-16phys map: Add tests for holes in MMIO region and orderMichael Neuling1-1/+27
This adds a couple of tests to ensure that there are no holes in the map for MMIO mappings and the map is sorted by start address. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-10Add tests for physical memory mapMichael Neuling2-0/+178
This adds a bunch of tests to the physical memory map infrastructure. It checks for overlaps and alignment.. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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