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2017-09-28cpu: idle POWER9 power management implementationNicholas Piggin1-1/+1
Add pm idle support to POWER9. IPIs are implemented with doorbells. POWER9 can use the EC=ESL=0 (lite) stop when sreset is not available. EC=ESL=1 state with RL=3 is enabled when we have a sreset wakeup. Deep idle states are not implemented. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19SLW: Removing timebase related flags for stop4Akshay Adiga1-2/+2
When a core enters stop4, it does not loose decrementer and time base. Hence removing flags OPAL_PM_DEC_STOP and OPAL_PM_TIMEBASE_STOP. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19SLW: Allow deep states if homer address is knownAkshay Adiga1-6/+17
Use a common variable has_wakeup_engine instead of has_slw to tell if the a) SLW image is populated in case of power8 b) CME image is populated in case of power9 Currently we expect CME to be loaded if homer address is known ( except for simulators) Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19SLW: Configure self-restore for HRMORAkshay Adiga1-0/+29
Make a stop api call using libpore to restore HRMOR register. HRMOR needs to be cleared so that when thread exits stop, they arrives at linux system_reset vector (0x100). Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19SLW: Add opal_slw_set_reg support for power9Akshay Adiga1-20/+40
This OPAL call is made from Linux to OPAL to configure values in various SPRs after wakeup from a deep idle state. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19Revert "hw/slw.c: Offline code still uses p8 bits"Stewart Smith1-3/+0
This reverts commit 0a2710381f34e6b4c03cff1fa76bc1b74f280ecd. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15hw/slw.c: Offline code still uses p8 bitsBalbir Singh1-0/+3
I'm seeing an infinite loop while hot unplugging a CPU. This is a workaround till we do the right things for p9. May be a candidate for backporting The messages I see in an infinite loop are: [ 740.250192896,3] LIBPORE: Core ID = 20 is not within valid range of [0;15] [ 740.250230176,3] SLW: Failed to set spr for CPU 51 When trying to hotunplug core id 20. For now the patch just skips calling p8_pore* on p9 machines. Signed-off-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-04idle: disable stop*_lite POWER9 idle states for Mambo platformNicholas Piggin1-1/+110
Mambo prior to Mambo.7.8.21 had a bug where the stop idle instruction with PSSCR[ESL]=PSSCR[EC]=0 would resume with MSR set as though it had taken a system reset interrupt. Linux currently executes this instruction with MSR already set that way, so the problem went unnoticed. A proposed patch to Linux changes that, and causes the idle code to crash. Work around this by disabling lite stop states for the mambo platform for now. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-04idle: user context state loss flags fix for stop statesNicholas Piggin1-4/+4
The "lite" stop variants with PSSCR[ESL]=PSSCR[EC]=1 do not lose user context, while the non-lite variants do (ESL: enable state loss). Some of the POWER9 idle states had these wrong. These are not used by Linux yet. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-24slw: Modify the power9 stop0_lite latency & residencyGautham R. Shenoy1-6/+6
Currently skiboot exposes the exit-latency for stop0_lite as 200ns and the target-residency to be 2us. However, the kernel cpu-idle infrastructure rounds up the latency to microseconds and lists the stop0_lite latency as 0us, putting it on par with snooze state. As a result, when the predicted latency is small (< 1us), cpuidle will select stop0_lite instead of snooze. The difference between these states is that snooze doesn't require an interrupt to exit from the state, but stop0_lite does. And the value 200ns doesn't include the interrupt latency. This shows up in the context_switch2 benchmark (http://ozlabs.org/~anton/junkcode/context_switch2.c) where the number of context switches per second with the stop0_lite disabled is found to be roughly 30% more than with stop0_lite enabled. =============================================================================== x latency_200ns_residency_2us + latency_200ns_residency_2us_stop0_lite_disabled N Min Max Median Avg Stddev x 100 222784 473466 294510 302295.26 45380.6 + 100 205316 609420 385198 396338.72 78135.648 Difference at 99.0% confidence 94043.5 +/- 23276.2 31.1098% +/- 7.69983% (Student's t, pooled s = 63892.8) =============================================================================== This can be correlated with the number of times cpuidle enters stop0_lite compared to snooze. =================================================================== latency=200ns, residency=2us stop0_lite enabled. * snooze usage = 7 * stop0 lite usage = 3200324 * stop1 lite usage = 6 stop0_lite disabled * snooze usage: 287846 * stop0_lite usage: 0 * stop1_lite usage: 0 ================================================================== Hence, bump up the exit latency of stop0_lite to 1us. Since the target residency is chosen to be 10 times the exit latency, set the target residency to 10us. With these values, we see a 50% improvement in the number of context switches: ===================================================================== x latency_200ns_residency_2us + latency_1us_residency_10us N Min Max Median Avg Stddev x 100 222784 473466 294510 302295.26 45380.6 + 100 281790 710784 514878 510224.62 85163.252 Difference at 99.0% confidence 207929 +/- 24858.3 68.7835% +/- 8.22319% (Student's t, pooled s = 68235.5) ===================================================================== The cpuidle usage statistics show that we choose stop0_lite less often in such cases. latency = 1us, residency = 10us stop0_lite enabled * snooze usage = 536808 * stop0 lite usage = 3 * stop1 lite usage = 7 Reported-by: Anton Blanchard <anton@samba.org> Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com> Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26Big log level reduction...Benjamin Herrenschmidt1-2/+2
90% of what we print isn't useful to a normal user. This dramatically reduces the amount of messages printed by OPAL in normal circumstances. We still need to add a way to bump the log level at boot based on a BMC scratch register or some HDAT property. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-19Ensure P9 DD1 workarounds apply only to NimbusMichael Neuling1-4/+5
The workarounds for P9 DD1 are only needed for Nimbus. P9 Cumulus will be DD1 but don't need these same workarounds. This patch ensures the P9 DD1 workarounds only apply to Nimbus. It also renames some things to make clear what's what. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-10pore: Always use libporeOliver O'Halloran1-25/+0
In the days of yore libpore was closed source and people wanted the option to not use it. That's no longer the case so lets ditch all the #ifdef crap. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-30SLW: Add init for power9 power managementAkshay Adiga1-7/+51
This patch adds new function to init core for power9 power management. SPECIAL_WKUP_* SCOM registers, if set, can hold the cores from going into idle states. Hence, clear PPM_SPECIAL_WKUP_HYP_REG scom register for each core during init. (This init are not required for MAMBO) Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-23slw: Define stop idle states for P9 DD1Shilpasri G Bhat1-4/+57
Only stop[0,1]_lite idle states are supported in DD1. And stop1 with ESL=EC=1 is used for CPU hotplug in DD1. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-16hw/slw: fix NOTICE/WARNING of idle states found/not-foundStewart Smith1-2/+2
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-02hw/slw: fix possible NULL dereferenceStewart Smith1-2/+8
Found by static analysis Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-02-22slw: Print enabled stop statesMichael Neuling1-0/+2
On boot, print the enabled stop states. Output looks like: [ 25.045201661,5] SLW: Enabling: stop0_lite [ 25.045205017,5] SLW: Enabling: stop0 [ 25.045206549,5] SLW: Enabling: stop1_lite [ 25.045208320,5] SLW: Enabling: stop1 [ 25.045209738,5] SLW: Enabling: stop2_lite [ 25.045211467,5] SLW: Enabling: stop2 Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-02-07slw: Fix parsing of supported STOP statesShilpasri G Bhat1-2/+4
Bits[0-15] are used to indicate the supported STOP states in "ibm,enabled-stop-levels" DT property and STOP0 is starting from Bit0. This patch fixes the parsing to read the appropriate bits. Fixes: c3ea33f173ec ("hw/slw: only enable supported STOP states") Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Reviewed-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-02-03slw: fix typo in slw dump commentJeremy Kerr1-1/+1
We have an typo in a @fwts-advice field, which means it's carried through to the generated fwts olog data. This change fixes the typo so that the advice output from fwts is correct. CC: Deb McLemore <debmc@linux.vnet.ibm.com> Reported-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Acked-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-01-16hw/slw: only enable supported STOP statesOliver O'Halloran1-0/+14
This patch adds parsing the ibm,enabled-stop-levels field when building the /ibm,opal/power-mgt/ node so that only the STOP levels that have been advertised by firmware are used. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-01-16hw/slw: use dt_new_check()Oliver O'Halloran1-3/+2
On P9 systems the /ibm,opal/power-mgt/ node may be created by the HDAT parser before reaching add_cpu_idle_state_properties(). This is fine, but it needs to be handled. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-12-13slw: Set PSSCR value for idle statesShilpasri G Bhat1-14/+78
PSSCR(Processor Stop Status and Control Register) is an SPR whose contents control the operation of stop instruction. Currently in DT, the value of PSSCR only included RL(Requested Level) for each idle state. This patch adds MTL(Maximum Transistion Level), TR(Transistion Rate), ESL(Enable State Loss) and EC(Exit Criterion) bits for idle state in the PSSCR configuration. It also adds new idle states stop0_lite, stop1_lite and stop2_lite which are no state loss versions of stop0, stop1 and stop2 respectively. The lite variant has EC and ESL bits of PSSCR set to 0. The thread entering a lite variant of stop state will not lose any state and will wakeup at next instruction following stop if MSR.EE=0 or at the corresponding interrupt handler if MSR.EE=1. This will reduce the exit latency of the idle state and hardware will not allocate the thread resources to other threads while in power saving mode. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-24slw: do SLW timer testing while holding xscom lockStewart Smith1-3/+9
We add some routines that let a caller get the xscom lock once and then do a bunch of xscoms while holding it. In some situations without this, it could take long enough to get the xscom lock that the 1ms timeout would expire and we'd falsely think the SLW timer didn't work when in fact it did. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-10-17Fast reboot for P8Benjamin Herrenschmidt1-2/+5
This is an experimental patch that implements "Fast reboot" on P8 machines. The basic idea is that when the OS calls OPAL reboot, we gather all the threads in the system using a combination of patching the reset vector and soft-resetting them, then cleanup a few bits of hardware (we do re-probe PCIe for example), and reload & restart the bootloader. For Trusted Boot, this means we *add* measurements to the TPM, so you will get *different* PCR values as compared to a full IPL. This makes sense as if you want to be sure you are running something known then, well, do a full IPL as soft reset should never be trusted to clear any malicious code. This is very experimental and needs a lot of testing and also auditing code for other bits of HW that might need to be cleaned up. BenH TODO: I also need to check if we are properly PERST'ing PCI devices. This is partially based on old code I had to do that on P7. I only support it on P8 though as there are issues with the PSI interrupts on P7 that cannot be reliably solved. Even though this should be considered somewhat experimental, we've had a lot of success on a variety of machines. Dozens/hundreds of reboots across Tuleta, Garrison and Habanero. Currently, we've hidden it behind a NVRAM config option, which *is* liable to change in the future (to ensure that only those who know what they're doing enable it) You can enable the experimental support via nvram option: nvram -p ibm,skiboot --update-config experimental-fast-reset=feeling-lucky Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: hide behind nvram option, include Mambo fixes from Mikey] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-09-17SLW: Actually print the register dump only to memoryStewart Smith1-1/+1
Fixes: 81154ba9b2d418cd5f9eda3a6f89ca6631556510 Reported-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-09-14slw: improve error message for SLW timer stuckStewart Smith1-3/+21
We still register dump, but only to in memory console buffer by default. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-08-22interrupts: Rename icp_prep_for_rvwinkle to icp_prep_for_pmBenjamin Herrenschmidt1-1/+1
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-08-22slw: Move SPR setup calls away from assemblyBenjamin Herrenschmidt1-0/+4
Move them to the C code so that rvwinkle_restore() is more generic and suitable for use for nap mode wakeup as well Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-08-22Rename rvwinkle patch to reset patch and install at bootBenjamin Herrenschmidt1-9/+7
The patch code itself is unchanged (for now...). Install it during boot so we will be able to use power management instructions. We can't just have a proper exception code built at 0x100 as this is otherwise one of our entry points. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-08-22Rename enter_rvwinkle to enter_pm_stateBenjamin Herrenschmidt1-4/+1
And add an argument to specify whether to enter nap or rvwinkle Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-07-11slw: fix not indented if conditionStewart Smith1-1/+1
found by Smatch static analysis (http://smatch.sourceforge.net/): hw/slw.c:687 add_cpu_idle_state_properties() warn: if statement not indented Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-06-30slw: FWTS annotation suggestion for SLWRegisterDumpStewart Smith1-4/+4
Suggested-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-06-30slw: Fix typo in FWTS annotationStewart Smith1-2/+2
Update copyright header date at the same time Suggested-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-06-24slw: add FWTS annotations for errorsStewart Smith1-0/+13
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-06-20slw: use strncpy instead of strcpyShreyas B. Prabhu1-1/+2
Use strncpy instead of strcpy while appending to name_buf. Suggested-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-06-20slw: Allow adding idle states to power-mgt node in mamboShreyas B. Prabhu1-6/+0
This patch removes the check which prevents adding any idle state to "power-mgt" node in mambo. Power8 exposes 3 idle states- nap, fast-sleep and deep-winkle. While fast-sleep depends on SCOMs and deep-winkle depends on SCOMs/SLW, nap has no such dependencies and it can be enabled in mambo. Current code checks for "fast-sleep" in hostboot provided "ibm,enabled-idle-states" dt node for adding fast-sleep and checks for presence of SLW for adding winkle to "power-mgt". Hence with this change only nap will be added to "power-mgt" node in mambo on Power8. On Power9, this patch enables all idle states which don't need SLW. Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-06-20slw: Move macros associated with power-mgt nodes to opal-api.hShreyas B. Prabhu1-76/+56
Move macros associated with cpuidle fields of power-mgt device tree nodes to opal-api.h This patch does not change any functionality. Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-06-20slw: Add Power9 idle states to power-mgt dt nodeShreyas B. Prabhu1-37/+149
POWER ISA v3 defines a new idle processor core mechanism. In summary, a) new instruction named stop is added. This instruction replaces instructions like nap, sleep, rvwinkle. b) new per thread SPR named PSSCR is added which controls the behavior of stop instruction. This SPR subsumes PMICR. This patch adds the supported idle states to power-mgt dt node. It also introduces ibm,cpu-idle-state-psscr and ibm,cpu-idle-state-psscr-mask entries which exposes the value to be written to PSSCR to enter a given stop state. These entries replaces POWER8's counterparts ibm,cpu-idle-state-pmicr and ibm,cpu-idle-state-pmicr-mask. Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-06-20slw: Remove unnecessary type casting castShreyas B. Prabhu1-6/+6
Suggested-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-06-20slw: Change variable name can_winkle to has_slwShreyas B. Prabhu1-4/+5
Change variable name "can_winkle" to a more generic name "has_slw". This makes it easier to add new deep-idle states which rely on SLW. Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-06-20slw: Simplify if-condition while adding idle states to device treeShreyas B. Prabhu1-30/+43
if-condition in add_cpu_idle_state_properties which checks if a given idle state is supported is bloated with multiple '&' and '||' operations. Simplify by adding a mask variable and setting the relevant bits. This patch does not change any functionality. Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-11-17slw: Remove overwrites for EX_PM_CORE_ECO_VRET and EX_PM_CORE_PFET_VRETShreyas B. Prabhu1-17/+0
Remove code where we overwrite EX_PM_CORE_ECO_VRET and EX_PM_CORE_PFET_VRET since they are being initialized in hostboot code. Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-11-17slw: don't be tricky with pointer mathStewart Smith1-3/+5
Mainly because this trips up some static analysis on resource usage and instead of having someone go back and prove it, add an assert and keep around a (no doubt optimized out) variable. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-11-10sparse: fix warning constant is so big it is long in hw/slw.cStewart Smith1-6/+6
hw/slw.c:485:26: warning: constant 0x0000002000000000 is so big it is long hw/slw.c:486:31: warning: constant 0x0000003000000000 is so big it is long Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-10-30slw: Move add_cpu_idle_state_properties() to add_opal_node()Shilpasri G Bhat1-3/+1
05f52a8dd7c7e402896e049fd24f83d56b70aff4 core: Setup the OPAL DT node before platform probe add_cpu_idle_state_properties() was made local to slw.c in the above commit which caused p7 systems to not populate the nap idle state in DT. So moving add_cpu_idle_state_properties() to add_opal_node to fix this bug. Reported-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-09-11slw/timer: SBE based timer supportBenjamin Herrenschmidt1-15/+168
Recent HostBoot & SBE firmware provide a HW timer facility that can be used to implement OPAL timers and thus limit the reliance on the Linux heartbeat. This implements support for it. The side effect is that i2c from Centaurs is now usable. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: fix run-timer unit test] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-08-31Fix scan-build waring of never read rc valueStewart Smith1-0/+4
Just log an error if we fail to re-read GP0. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-07-31errorlog: Deprecate elog callback parameterSamuel Mendoza-Jonas1-4/+4
There are now no users of the call_out parameter and future users should use the log_append_msg() and log_append_data() functions, so remove all references to call_out. Signed-off-by: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-07-02fixup warnings when building with PORE=0Stewart Smith1-7/+15
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
generated by cgit v1.1 at 2024-09-09 01:23:59 +0000