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2019-07-26SPDX-ify all skiboot codeStewart Smith1-16/+4
Use Software Package Data Exchange (SPDX) to indicate license for each file that is unique to skiboot. At the same time, ensure the (C) who and years are correct. See https://spdx.org/ Signed-off-by: Stewart Smith <stewart@linux.ibm.com> [oliver: Added a few missing files] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-06-24Separate FSP specific PSI codeStewart Smith1-85/+9
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-06-04Remove POWER7 and POWER7+ supportStewart Smith1-103/+2
It's been a good long while since either OPAL POWER7 user touched a machine, and even longer since they'd have been okay using an old version rather than tracking master. There's also been no testing of OPAL on POWER7 systems for an awfully long time, so it's pretty safe to assume that it's very much bitrotted. It also saves a whole 14kb of xz compressed payload space. Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Enthusiasticly-Acked-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-05-15Add P9 DIO interrupt supportLei YU1-0/+2
On P9 there are GPIO port 0, 1, 2 for GPIO interrupt, and DIO interrupt is used to handle the interrupts. Add support to the DIO interrupts: 1. Add dio_interrupt_register(chip, port, callback) to register the interrupt; 2. Add dio_interrupt_deregister(chip, port, callback) to deregister; 3. When interrupt on the port occurs, callback is invoked, and the interrupt status is cleared. Signed-off-by: Lei YU <mine260309@gmail.com> [oliver: Fixed Makefile.inc merge conflict] Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-01-25Remove POWER9N DD1 supportNicholas Piggin1-37/+6
This is not a shipping product and is no longer supported by Linux or other firmware components. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-06-27occ: Move occ declarations into occ.hAndrew Donnellan1-0/+1
OCC declarations are currently split between skiboot.h and occ-sensor.h. Given the growing unwieldyness of skiboot.h it's probably time to move it all into one header. Rename occ-sensor.h to occ.h, move all OCC-related declarations out of skiboot.h, and add #includes as necessary. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-06-18psi: Properly mask errors in SEMRJoel Stanley1-1/+1
It looks like this code intended to read PSIHB SEMR, mask out some of the values, and write it back. Instead it writes the mask to the register. Found using scan-build. Fixes: 39addc6a0f1f ("PSI: Reorganize PSI link down handling code") Signed-off-by: Joel Stanley <joel@jms.id.au> Acked-by: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-04-30Add SBE driver supportVasant Hegde1-1/+1
SBE (Self Boot Engine) on P9 has two different jobs: - Boot the chip up to the point the core is functional - Provide various services like timer, scom, stash MPIPL, etc., at runtime OPAL can communicate to SBE via a set of data and control registers provided by the PSU block in P9 chip. - Four 8 byte registers for Host to send command packets to SBE - Four 8 byte registers for SBE to send response packets to Host - Two doorbell registers (1 on each side) to alert either party when data is placed in above mentioned data register Protocol constraints: Only one command is accepted in the command buffer until the response for the command is enqueued in the response buffer by SBE. Usage: We will use SBE for various purposes like timer, MPIPL, etc. This patch implements the SBE MBOX spec for OPAL to communicate with SBE. Design consideration: - Each chip has SBE. We need to track SBE messages per chip. Hence added per chip sbe structure and list of messages to that chip - SBE accepts only one command at a time. Hence serialized MBOX commands. - OPAL gets interrupted once SBE sets doorbell register - OPAL has to clear doorbell register after reading response - Every command class has timeout option. Timed out messages are discarded - SBE MBOX commands can be classified into four types : - Those that must be sent to the master only (ex: sending MDST/MDDT info) - Those that must be sent to slaves only (ex: continue MPIPL) - Those that must be sent to all chips (ex: close insecure window) - Those that can be sent to any chip (ex: timer) Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-04-11interrupts: Create an "interrupts" property in the OPAL nodeBenjamin Herrenschmidt1-3/+3
Deprecate the old "opal-interrupts", it's still there, but the new property follows the standard and allow us to specify whether an interrupt is level or edge sensitive. Similarly create "interrupt-names" whose content is identical to "opal-interrupts-names". Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2017-06-26Big log level reduction...Benjamin Herrenschmidt1-2/+2
90% of what we print isn't useful to a normal user. This dramatically reduces the amount of messages printed by OPAL in normal circumstances. We still need to add a way to bump the log level at boot based on a BMC scratch register or some HDAT property. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26psi: Switch to ESB mode laterBenjamin Herrenschmidt1-4/+4
There's an errata, if we switch to ESB mode before setting up the various ESB mode related registers, a pending interrupts can go wrong. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26psi: Use phys_map to setup the BARsBenjamin Herrenschmidt1-31/+21
Removes the hard coded address and the useless warning Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-19Ensure P9 DD1 workarounds apply only to NimbusMichael Neuling1-10/+11
The workarounds for P9 DD1 are only needed for Nimbus. P9 Cumulus will be DD1 but don't need these same workarounds. This patch ensures the P9 DD1 workarounds only apply to Nimbus. It also renames some things to make clear what's what. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-08SBE: Add passthrough command supportVasant Hegde1-1/+2
SBE sends passthrough command. We have to capture this interrupt and send event to HBRT via opal-prd (user space daemon). This patch adds minimal SBE code to capture SBE interrupt and send event to opal-prd. Next patch will add opal-prd (user space) support. CC: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-04-12occ/irq: Fix SCOM address and irq reasons for P9 OCCShilpasri G Bhat1-2/+2
This patch fixes the SCOM address for OCC_MISC register which is used for OCC interupts. In P9, OCC sends an interrupt to notify change in the shared memory like throttle status. This patch handles this interrupt reason. Originally-from: Michael Neuling <mikey@neuling.org> Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org>
2017-03-03lpc/uart: Support routing of selected LPC interrupts to LinuxBenjamin Herrenschmidt1-8/+16
Each LPC interrupt can be routed to one of 4 lines to the PSI bridge which represent 4 different system interrupts. This allows LPC clients to request as specific target (Linux or OPAL) and makes the LPC core pick a route and configure it appropriately. The UART is updated to properly forward interrupts to Linux if necessary Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-02-07xive/psi/lpc: Handle proper clearing of LPC SerIRQ latch on DD1Benjamin Herrenschmidt1-3/+38
On DD1, the LPC SerIRQ are latched to 1 in HW but never back to 0, we need an explicit clear after running the handler. (Not before as they are level interrupts, they will be latched again if they are still pending). For now we do that in lpc_dispatch_ser_irqs() but that only works for interrupts routed to OPAL. In order to support routing LPC interrutps to Linux, we need a custom EOI handler that does the clearing of the latch before we do the EOI in the ESB. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-01-05psi: Add names for PSI interruptsBenjamin Herrenschmidt1-0/+48
This adds a name callback to the PSI interrupts sources on P8 and P9 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-12-21tree-wide: use dt_add_property_u64s() where we canOliver O'Halloran1-1/+1
A few places (mostly old code) were using: add_property_cells(hi32(number), lo32(number)); This patch converts them to use the helper rather than doing it manually. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-12-16psi: fix the xive registers initialization on P8Cédric Le Goater1-12/+8
When skiboot initializes PSIHB, it fills the xive registers with server=0, prio=0xff. The source (irq) value is left shifted by 29 bits and the last two xive registers (irq 4 and 5) are set with a bogus value : write 0x30 val 0x000000ff00000000 write 0x60 val 0x000000ff20000000 write 0x68 val 0x000000ff40000000 write 0x70 val 0x000000ff60000000 write 0x78 val 0xffffffff80000000 write 0x80 val 0xffffffffa0000000 which seems to be fine for real HW but causes a lof of pain under qemu. Let's use an 'unsigned' type to initialize the xive registers and also use a loop on the PSI irq numbers, like it is done in psi_cleanup_irq. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15xive: Provide a way to override some IPI sourcesBenjamin Herrenschmidt1-3/+3
Some devices such as NX or the NPU will use some of the XIVE provided IPIs for their own interrupts. Thus we need a way for those to provide a custom irq_source_ops for portions of the IPI space in order for them to provide their own attributes() and if needed, interrutps() callbacks. We achieve that by creating a second list of sources which can overlap the primary. The global stock of IPIs is registered by XIVE in the secondary list which is searched when no match is found in the primary. A new API xive_register_ipi_source() is provided for those devices to create an overlapping source structure in the primary list for a subset of the IPIs. Those IPIs must have been previously allocated using xive_alloc_ipi_irqs() Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15psi: Fix P9 BAR setup on multi-chipsBenjamin Herrenschmidt1-2/+4
We need to inject the chip id in the MMIO address Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-11-15psi: Add DT option to disable LPC interruptsBenjamin Herrenschmidt1-1/+22
Some sim models have the LPC interrupts stuck asserted on secondary chips so we add a device-tree option that makes us set the policy for these to "Linux" instead of "OPAL". Since they aren't referenced in the device-tree this will de-facto prevent them from being enabled Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-10-17Fast reboot for P8Benjamin Herrenschmidt1-60/+43
This is an experimental patch that implements "Fast reboot" on P8 machines. The basic idea is that when the OS calls OPAL reboot, we gather all the threads in the system using a combination of patching the reset vector and soft-resetting them, then cleanup a few bits of hardware (we do re-probe PCIe for example), and reload & restart the bootloader. For Trusted Boot, this means we *add* measurements to the TPM, so you will get *different* PCR values as compared to a full IPL. This makes sense as if you want to be sure you are running something known then, well, do a full IPL as soft reset should never be trusted to clear any malicious code. This is very experimental and needs a lot of testing and also auditing code for other bits of HW that might need to be cleaned up. BenH TODO: I also need to check if we are properly PERST'ing PCI devices. This is partially based on old code I had to do that on P7. I only support it on P8 though as there are issues with the PSI interrupts on P7 that cannot be reliably solved. Even though this should be considered somewhat experimental, we've had a lot of success on a variety of machines. Dozens/hundreds of reboots across Tuleta, Garrison and Habanero. Currently, we've hidden it behind a NVRAM config option, which *is* liable to change in the future (to ensure that only those who know what they're doing enable it) You can enable the experimental support via nvram option: nvram -p ibm,skiboot --update-config experimental-fast-reset=feeling-lucky Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: hide behind nvram option, include Mambo fixes from Mikey] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-08-11psi: On p9, create an interrupt-map for routing PSI interruptsBenjamin Herrenschmidt1-0/+15
This will provide the global IRQ numbers for all 16 PSI inputs (though we don't really care about 0 here). We can then express them in the device-tree as relative to the PSI bridge. Among others, that allows us to express the external interrupt and the LPC interrupt using a fixed numbering scheme. The example device-tree is updated to route them all to the LPC0 input which corresponds to what the LPC code does at the moment. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-08-11psi: Ensure chip_id is always set properlyBenjamin Herrenschmidt1-14/+10
Also fix an error path that can dereference a NULL PSI pointer Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-08-11psi: Remove psi->workingBenjamin Herrenschmidt1-13/+1
I was only ever set to true Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-08-11lpc: Add P9 LPC interrupts supportBenjamin Herrenschmidt1-1/+1
We currently don't exploit the new MUX that allow to spread them around different PSI interrupts, they all go to LPC#0 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-08-11psi: Add P9 supportBenjamin Herrenschmidt1-147/+278
This reworks interrupt handling a bit and adds support for XIVE based interrupts and the new sources available on POWER9. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-08-11interrupts: Add new source ->attributes callbackBenjamin Herrenschmidt1-24/+27
This allows a given source to provide per-interrupt attributes such as whether it targets OPAL or Linux and it's estimated frequency. The former allows to get rid of the double set of ops used to decide which interrupts go where on some modules like the PHBs and the latter will be eventually used to implement smart caching of the source lookups. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-07-13interrupts: Expose irq_source and change prototypes of all opsBenjamin Herrenschmidt1-14/+15
This makes irq_source public, and change all irq_source_ops to take the source pointer as a first argument (they can still dig the void * data out of that). This will allow us to embed/wrap it for XIVE later on. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-07-12interrupts: Use a #interrupt-cells of 2 for XICS interruptsBenjamin Herrenschmidt1-1/+1
This is more compliant with PAPR, it will also allow us to use the second cell for other attributes on P9. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-11-10sparse: fix warning constant is so big it is long in hw/psi.cStewart Smith1-1/+1
hw/psi.c:526:24: warning: constant 0x000000ff00000000 is so big it is long Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-09-11psi: Fix a few typosBenjamin Herrenschmidt1-6/+6
Nothing critical, no functional changes. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-07-31errorlog: Deprecate elog callback parameterSamuel Mendoza-Jonas1-1/+1
There are now no users of the call_out parameter and future users should use the log_append_msg() and log_append_data() functions, so remove all references to call_out. Signed-off-by: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-05-13occ: Send self-interrupt to chip with active PSIJoel Stanley1-0/+7
We were previously asking the OCC of the current chip to generate the self interrupt. If Hostboot does not configure all the PSI Host Bridges, so if the current chip happens to have an unconfigured PSI HB, the chip will never see the interrupt. Instead grab a chip id from the list of configured PSIs, and ask the OCC on that chip to generate the self-interrupt. This adds a pointer to the chip's PSI in struct proc_chip so we can use the current chip's PSI if it is active without having to look through all of them. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-04-01Remove redundant includes of opal-api.hMichael Ellerman1-1/+0
Now that opal.h includes opal-api.h, there are a bunch of files that include both but don't need to. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-03-04hw/prd: Add firmware PRD handling subsystemJeremy Kerr1-1/+1
This change adds Processor Recovery Diagnostics (PRD) code to skiboot firmware. This allows certain hardware RAS events to be handled by a userspace application. The core of the PRD code is a messaging interface to the kernel (and onwards to userspace). PRD events are logged with the prd.c code, and sent to the kernel as opal_msg messages. For responses to these messages, the kernel will reply using a new OPAL call, opal_prd_msg. Only one message is outstanding at a time; we collect events from hardware interrupts (hooked up by subsequent patches), and set per-processor event bits. Once an event has been consumed by the kernel, we clear that event from out pending set, and send any further pending events. Certain events (hardware attentions from the psi layer) need to be masked at interrupt time. For these, we have an acknowledgement facility to clear the mask once the userspace PRD application has cleared the source of the error. Includes multiple contributions from: Neelesh Gupta <neelegup@linux.vnet.ibm.com> Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Neelesh Gupta <neelegup@linux.vnet.ibm.com> Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-02-26sparse: psi_link_poll_active can be staticCédric Le Goater1-1/+1
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-02-10PSI: Revert the timeout for PSI link recovery to architected valueAnanth N Mavinakayanahalli1-1/+1
The architected value for the PSI link to come back up is 30 minutes. In OPAL, we currently only wait 15 minutes before logging an error. Fix that... Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-02-09PSI: Report a PEL for PSI timeoutAnanth N Mavinakayanahalli1-3/+9
We currently just log an error when we don't find an active PSI link 15 minutes after it went down. Add a PEL log, with sufficient severity so it gets pushed to the administrator. V2: Reset the timeout correctly to prevent error log flooding. Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com> Tested-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-02-06Move skiboot internal things from opal.h to opal-api.hStewart Smith1-0/+1
This is probably not the best collection of things in the world, but it means that opal.h is much closer to being directly usable by an OS. This triggers a bunch of #include fixes throughout the tree. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2014-12-05occ: Fix clearing of OCC interrupt on remote fixBenjamin Herrenschmidt1-1/+1
If the OCC interrupt comes from another chip, we incorrectly try to clear it on the local one. This causes hangs at boot on some machines. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2014-11-12i2c: Use new timer facility and improve interrupts handlingBenjamin Herrenschmidt1-2/+10
We only poll the masters for the chip that got the interrupt and we improve the running of the timers as well. We user the new TIMER_POLL facility to replace the use of the OPAL poller, which simplifies the code further. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-10-27hw/i2c: i2c driver infrastructure providing device I/ONeelesh Gupta1-1/+2
This patch adds the generic i2c driver infrastructure to handle multiple i2c master cores present in the system and exposes structures and interfaces for the client to perform I/O on the i2c slave devices. The driver adds the capability to queue multiple requests from client and let clients notified asynchronously after completion. It does that by handling the i2c interrupt or through OPAL poller in the absence of interrupt. Signed-off-by: Neelesh Gupta <neelegup@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2014-10-24irq/occ/opal: Add self-sent dummy interruptBenjamin Herrenschmidt1-1/+1
This makes OPAL use the OCC interrupt facility to send itself an interrupt whenever the OPAL event bit is set as a result of an OPAL call that wasn't itself opal_handle_interrupt() or opal_handle_hmi() (both of which we know the OS will already deal with appropriately). This ensures that OPAL event changes are notified to Linux via its interrupt path which is necessary for it to properly broadcast the state change to its various clients. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-10-22PSI: Drive link down on HIRAnanth N Mavinakayanahalli1-31/+34
After sending the FSP reset sequence via PSIHBCR, drive the PSI link down without actually waiting for the PSI interrupt indicating the 'Link Inactive Transition'. There have been cases where this interrupt doesn't arrive and we are left high and dry waiting for it, while the FSP comes back up and thinks Sapphire is not initializing the new link (bz 117526 for instance). Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2014-10-08remove unused DBG and FSP_TRACE macros from hw/psi.cStewart Smith1-4/+0
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2014-09-23psi: Workaround for "pulse" external interruptBenjamin Herrenschmidt1-0/+12
The FPGA used on some open power machines generates regular pulses instead of levels. In that case, reading the status might fail since it's not latched. In that case, also check the latched event bit in the XIVR. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-07-25PSI: Fix PSI driven FSP reset sequenceAnanth N Mavinakayanahalli1-4/+14
This patch will fix the flow of triggering actual reset of the FSP. Host should follow the following steps to reset FSP. 1.) Reading the HBC register 2.) Turning on bit 6 and writing the register (fsp reset) 3.) reading the register back 4.) clearing bit 6 and writing the register (clear fsp reset) Test results: Initiate HIR on FSP with the following commands 1) fsptelinit --disablerecovery 2) putmemproc 300000f8 0x00000000deadbeef Sapphire traces: SURV: Heartbeat Acknowledgment error from FSP ELOG: Notified of log 0x50294535 (size: 6356) FSPLED: FSP_CMD_SET_LED_STATE command received ELOG: Notified of log 0x50294566 (size: 2708) FSPLED: FSP_CMD_GET_LED_STATE command received FSPLED: FSP_CMD_SET_LED_STATE command received ELOG: Notified of log 0x50294629 (size: 2744) SURV: [ 9be1a4cc2e] Surv ACK timed out; initiating R/R FSP: fsp_trigger_reset() entry FSP: Writing reset to DRCR FSP: DRCR changed, old = 0, new = 8100 SURV: [ 9c1f97eccd] Sending the hearbeat command to FSP FSP: DRCR changed, old = 8100, new = 0 FSP: DRCR ack received. Triggering reset PSI: Driving FSP reset via PSI PSI[0x000]: FSP reset start PSIHBCR set to def0300000000000 PSI[0x000]: FSP reset complete. PSIHBCR set to dcf0300000000000 PSI[0x000]: PSI mgmnt interrupt CR=0xdcf09100c0000000 PSI: PSI Reported Error PSI: PSI Link Inactive Transition PSI: SEMR set to fff0fff00000 PSI[0x000]: Disabling link! PSI: PSIHB_CR (error bits) set to 48f0110040000000 PSI: starting link polling FSP #0: Link down, starting R&R FSPCON: Closed consoles on account of FSP reset/reload SURV: Disabling surveillance FSP: Closing NVRAM on account of FSP Reset PSI[0x000]: Poll CR=0x48f0100040000000 PSI[0x000]: Poll CR=0x48f0100040000000 PSI[0x000]: Poll CR=0x48f0100040000000 PSI[0x000]: Poll CR=0x48f0100040000000 PSI[0x000]: Poll CR=0x48f0100040000000 ... .... PSI[0x000]: Poll CR=0x48f0100040000000 PSI[0x000]: Poll CR=0x48f0100040000000 PSI[0x000]: Poll CR=0x48f0100040000000 PSI[0x000]: Poll CR=0x48f0100040000000 PSI[0x000]: Poll CR=0xccf0300000000000 PSI[0x000]: Found active link! PSI: stopping link polling FSP: Connected to FSP-A FSP #0: DISR stat change = 0x00000029 FSP #0: DISR stat change = 0x00000201 FSP #0: Detected R&R complete, acking FSP #0: DISR stat change = 0x00000001 FSP: FSP assuming new role FSP: Unhandled message ce0900 FSP: SP says Reset/Reload complete DUMP: FipS dump available. ID = 0x6a000036 [size: 36086215 bytes] FSP: Reassociating HVSI console 1 FSP: Reassociating HVSI console 2 SURV: Querying FSP's surveillance status FSP: Reopening NVRAM of FSP Reload complete FSP NVRAM: Opening nvram... MDST: Table updated. FSPCON: Got HMC interface query SURV: Received heartbeat acknowledge from FSP FSP: FSP query capabilities After reset, FSP reached runtime state. $ smgr mfgState runtime On FSP, HIR resgister set to 1 and reset reload is zero. $ registry -l smgr smgr/rr_count_hostinitiated: 0001 [..] smgr/rr_count_other: 0000 [..] Signed-off-by: Mamatha Inamdar <mamatha4@linux.vnet.ibm.com> Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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