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2019-07-26hw/phys-map: Add Axone memory mapReza Arbab1-3/+138
Add the physical memory map for Axone systems. According to 'make hw-check', there are no holes or overlapping regions. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Acked-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Acked-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26hw/phys-map: Add pvr argument to phys_map_init()Reza Arbab1-1/+1
When new chip types are added, phys_map_init() will need to know which memory map it should use. Instead of directly checking PVR, make it an argument to the function, so that 'make hw-check' can test all the maps. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Acked-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Acked-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26SPDX-ify all skiboot codeStewart Smith1-13/+4
Use Software Package Data Exchange (SPDX) to indicate license for each file that is unique to skiboot. At the same time, ensure the (C) who and years are correct. See https://spdx.org/ Signed-off-by: Stewart Smith <stewart@linux.ibm.com> [oliver: Added a few missing files] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-05-20hw/npu2-opencapi: Add initial support for allocating OpenCAPI LPC memoryAndrew Donnellan1-0/+11
Lowest Point of Coherency (LPC) memory allows the host to access memory on an OpenCAPI device. Define 2 OPAL calls, OPAL_NPU_MEM_ALLOC and OPAL_NPU_MEM_RELEASE, for assigning and clearing the memory BAR. (We try to avoid using the term "LPC" to avoid confusion with Low Pin Count.) At present, we use a fixed location in the address space, which means we are restricted to a single range of 4TB, on a single OpenCAPI device per chip. In future, we'll use some chip ID extension magic to give us more space, and some sort of allocator to assign ranges to more than one device. Signed-off-by: Andrew Donnellan <ajd@linux.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-02-13hw/phys-map: Add missing newline in log outputReza Arbab1-1/+1
The call to prlog() here is missing a \n. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-15npu2: Move to new GPU memory mapMichael Neuling1-0/+5
There are three different ways we configure the MCD and memory map. 1) Old way (current way) Skiboot configures the MCD and puts GPUs at 4TB and below 2) New way with MCD Hostboot configures the MCD and skiboot puts GPU at 4TB and above 3) New way without MCD No one configures the MCD and skiboot puts GPU at 4TB and below The patch keeps option 1 and adds options 2 and 3. The different configurations are detected using certain scoms (see patch). Option 1 will go away eventually as it's a configuration that can cause xstops or data integrity problems. We are keeping it around to support existing hostboot. Option 2 supports only 4 GPUs and 512GB of memory per socket. Option 3 supports 6 GPUs and 4TB of memory but may have some performance impact. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-15phys-map: Rename GPU_MEM to GPU_MEM_4T_DOWNMichael Neuling1-7/+7
This map is soon to be replaced, but we are going to keep it around for a little while so that we support older hostboot firmware. Rename it for now. Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26Big log level reduction...Benjamin Herrenschmidt1-1/+1
90% of what we print isn't useful to a normal user. This dramatically reduces the amount of messages printed by OPAL in normal circumstances. We still need to add a way to bump the log level at boot based on a BMC scratch register or some HDAT property. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-26psi: Use phys_map to setup the BARsBenjamin Herrenschmidt1-1/+1
Removes the hard coded address and the useless warning Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-16hw/phys_map: Use GCIDs as a chip indexOliver O'Halloran1-4/+5
Currently we pass in a proc_chip structure to phys_map_get(). All we we really need from this structure is the Global Chip ID (GCID). This patch reworks the function so that we only need to pass the GCID which allows us to use it before the proc_chip structures have been initialised (i.e in the HDAT parser). Cc: Michael Neuling <mikey@neuling.org> Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Acked-By: Michael Neuling <mikey@neuling.org> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-16phys map: Remove hole in NPU sectionMichael Neuling1-10/+10
When we first added the map, we accidentally left a hole after the NPU PHY regs region. Fix this hole. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-16phys map: Add missing NPU user regs regionMichael Neuling1-0/+1
We don't use this region currrently but we should add for completeness. Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-10phb4: Increase 64bit MMIO BAR size from 128GB to 256GBMichael Neuling1-7/+7
Primarily for GPUs which may have large MMIO space for frame buffers. This shuffles the memory map around a bit and starts using the 2TB region. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-10Add global physical memory mapMichael Neuling1-0/+199
This adds a global map for allocating physical memory address. This centralises physical memory space allocations into one location rather than spread through, PHB, XIVE, NX etc. This adds a new call phys_map_get() which takes a chip, type and index and returns a address and size for the region to be used. An error in a call to this function crashes skiboot. This is done since bogus calls here are going to be hit by developers not users and they need to be fixed. Currently only P9 is implemented but other chips should be easy to add. On P9 BARs are generally set by skiboot. On P8 this was done by hostboot so this is not needed there. This just adds the infrastructure. User (PHB4, XIVE etc) will be migrated in subsequent patches. Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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