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2018-04-04xive: disable store EOI supportCédric Le Goater1-4/+14
Hardware has limitations which would require to put a sync after each store EOI to make sure the MMIO operations that change the ESB state are ordered. This is a killer for performance and the PHBs do not support the sync. So remove the store EOI for the moment, until hardware is improved. Also, while we are at changing the XIVE source flags, let's fix the settings for the PHB4s which should follow these rules : - SHIFT_BUG for DD10 - STORE_EOI for DD20 and if enabled - TRIGGER_PAGE for DDx0 and if not STORE_EOI Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> (cherry picked from commit 19335bbf77d85bcaf74c037efef9f0e7e76cf227) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-02-22phb4: Disable lane eq when retrying some nvidia GEN3 devicesMichael Neuling1-9/+45
This fixes these nvidia cards training at only GEN2 spends rather than GEN3 by disabling PCIe lane equalisation. Firstly we check if the card is in a whitelist. If it is and the link has not trained optimally, retry with lane equalisation off. We do this on all POWER9 chip revisions since this is a device issue, not a POWER9 chip issue. Signed-off-by: Michael Neuling <mikey@neuling.org> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-02-20phb3/phb4/p7ioc: Document supported TCE sizes in DTRussell Currey1-0/+5
Add a new property, "ibm,supported-tce-sizes", to advertise to Linux how big the available TCE sizes are. Each value is a bit shift, from smallest to largest. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-02-20phb4: Fix TCE page sizeRussell Currey1-4/+4
The page sizes for TCEs on P9 were inaccurate and just copied from PHB3, so correct them. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-02-14phb4: Only escalate freezes on MMIO load where necessaryRussell Currey1-1/+24
In order to work around a hardware issue, MMIO load freezes were escalated to fences on every chip. Now that hardware no longer requires this, restrict escalation to the chips that actually need it. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-02-13capi: Enable channel tag streaming for PHB in CAPP modeVaibhav Jain1-8/+4
We re-enable channel tag streaming for PHB in CAPP mode as without it PEC was waiting for cresp for each DMA write command before sending a new DMA write command on the Powerbus. This resulted in much lower DMA write performance than expected. The patch updates enable_capi_mode() to remove the masking of channel_streaming_en bit in PBCQ Hardware Configuration Register. Also does some re-factoring of the code that updates this register to use xscom_write_mask instead of xscom_read followed by a xscom_write. Cc: stable Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Christophe Lombard clombard@linux.vnet.ibm.com Acked-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-02-08capi: Fix the max tlbi divider and the directory size.Christophe Lombard1-2/+3
Switch to 512KB mode (directory size) as we don’t use bit 48 of the tag in addressing the array. This mode is controlled by the Snoop CAPI Configuration Register. Set the maximum of the number of data polls received before signaling TLBI hang detect timer expired. The value of '0000' is equal to 16. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-30capi: Disable CAPP virtual machinesVaibhav Jain1-0/+1
When exercising more than one CAPI accelerators simultaneously in cache coherency mode, the verification team is seeing a deadlock. To fix this a workaround of disabling CAPP virtual machines is suggested. These 'virtual machines' let PSL queue multiple CAPP commands for servicing by CAPP there by increasing throughput. Below is the error scenario described by the h/w team: " With virtual machines enabled we had a deadlock scenario where with 2 or more CAPI's in a system you could get in a deadlock scenario due to cast-outs that are required break the deadlock (evict lines that another CAPI is requesting) get stuck in the virtual machine queue by a command ahead of it that is being retried by the same scenario in the other CAPI. " So this patch updates CAPP APC Master Powerbus control register during CAPP init to also set Bit(12) that disables CAPP virtual machines. This forces processing of CAPP commands from PSL one at a time and thereby preventing above mentioned deadlock scenario. Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-30capi: Perform capp recovery sequence only when PBCQ is idleVaibhav Jain1-3/+4
Presently during a CRESET the CAPP recovery sequence can be executed multiple times in case PBCQ on the PEC is still busy processing in/out bound inflight transactions. This patch updates phb4_creset() to perform capp-recovery sequence via do_capp_recovery_scoms() only when PBCQ General Status Register reports no pending transactions. Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Christophe Lombard clombard@linux.vnet.ibm.com Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-01-14phb4: Dump CAPP error registers when it asserts link downVaibhav Jain1-5/+31
This patch introduces a new function phb4_dump_app_err_regs() that dumps CAPP error registers in case the PEC nestfir register indicates that the fence was due to a CAPP error (BIT-24). Contents of these registers are helpful in diagnosing CAPP issues. Registers that are dumped in phb4_dump_app_err_regs() are: * CAPP FIR Register * CAPP APC Master Error Report Register * CAPP Snoop Error Report Register * CAPP Transport Error Report Register * CAPP TLBI Error Report Register * CAPP Error Status and Control Register Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Christophe Lombard<clombard@linux.vnet.ibm.com> Acked-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-11phb4: Change PCI MMIO timersMichael Neuling1-2/+2
Currently we have a mismatch between the NCU and PCI timers for MMIO accesses. The PCI timers must be lower than the NCU timers otherwise it may cause checkstops. This changes PCI timeouts controlled by skiboot to 33-50ms. It should be forwards and backwards compatible with expected hostboot changes to the NCU timer. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-30phb4: Change default GEN3 lane equalisation setting to 0x54Michael Neuling1-2/+2
Currently our GEN3 lane equalisation settings are set to 0x77. Change this to 0x54. This change will allow us to train at GEN3 in a shorter time and more consistently. This setting gives us a TX preset 0x4 and RX hint 0x5. This gives a boost in gain for high frequency signaling. It allows the most optimal continuous time linear equalizers (CTLE) for the remote receiver port and de-emphasis and pre-shoot for the remote transmitter port. Machine Readable Workbooks (MRW) are moving to this new value also. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-30phb4: Init changesMichael Neuling1-6/+6
These init changes for phb4 from the HW team. Link down are now endpoint recoverable (ERC) rather than PHB fatal errors. BLIF Completion Timeout Error now generate an interrupt rather than causing freeze events. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-15phb4: Fix lane equalisation settingMichael Neuling1-1/+1
Fix cut and paste from phb3. The sizes have changes now we have GEN4, so the check here needs to change also Without this we end up with the default settings (all '7') rather than what's in HDAT. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-15phb4: Fix PE mapping of M32 BARBenjamin Herrenschmidt1-13/+11
The M32 BAR is the PHB4 region used to map all the non-prefetchable or 32-bit device BARs. It's supposed to have its segments remapped via the MDT and Linux relies on that to assign them individual PE#. However, we weren't configuring that properly and instead used the mode where PE# == segment#, thus causing EEH to freeze the wrong device or PE#. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-15phb4: Fix lost bit in PE number on config accessesBenjamin Herrenschmidt1-3/+3
A PE number can be up to 9 bits, using a uint8_t won't fly.. That was causing error on config accesses to freeze the wrong PE. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-13phb4: Update initsMichael Neuling1-1/+1
New init value from HW folks for the fence enable register. This clears bit 17 (CFG Write Error CA or UR response) and bit 22 (MMIO Write DAT_ERR Indication) and sets bit 21 (MMIO CFG Pending Error) Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-09capi: move the acknowledge of the HMI interruptChristophe Lombard1-4/+4
We need to acknowledge an eventual HMI initiated by the previous forced fence on the PHB to work around a non-existent PE in the phb4_creset() function. For this reason do_capp_recovery_scoms() is called now at the beginning of the step: PHB4_SLOT_CRESET_WAIT_CQ Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Acked-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-11-09capi: update ci store buffers and dma enginesChristophe Lombard1-37/+68
The number of read (APC type traffic) and mmio store (MSG type traffic) resources assigned to the CAPP is controlled by the CAPP control register. According to the type of CAPI cards present on the server, we have to configure differently the CAPP messages and the DMA read engines given to the CAPP for use. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Acked-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-23phb4: Escalate freeze to fence to avoid checkstopMichael Neuling1-6/+45
Freeze events such as MMIO loads can cause the PHB to lose it's limited powerbus credits. If all credits are used and a further MMIO will cause a checkstop. To work around this, we escalate the troublesome freeze events to a fence. The fence will cause a full PHB reset which resets the powerbus credits and avoids the checkstop. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-23phb4: Move code to find frozen PE earlierMichael Neuling1-14/+13
We are going to reuse this so move it earlier. No functional change Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-23phb4: Update some init registersMichael Neuling1-3/+3
New inits based on next PHB4 workbook. Increases some timeouts to avoid some spurious error conditions. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-23phb4: Enable PHB MMIO in phb4_root_port_init()Michael Neuling1-2/+2
Linux EEH flow is somewhat broken. It saves the PCIe config space of the PHB on boot, which it then uses to restore on EEH recovery. It does this to restore MMIO bars and some other pieces. Unfortunately this save is done before any drivers are bound to devices under the PHB. A number of other things are configured in the PHB after drivers start, hence some configuration space settings aren't saved correctly. These include bus master and MMIO bits in the command register. Linux tried to hack around this in this linux commit bf898ec5cb powerpc/eeh: Enable PCI_COMMAND_MASTER for PCI bridges This sets the bus master bit but ignores the MMIO bit. Hence we lose MMIO after a full PHB reset. This causes the next MMIO access to the device to fail and for us to perform a PE freeze recovery, which still doesn't set the MMIO bit and hence we still fail. This works around this by forcing MMIO on during phb4_root_port_init(). With this we can recovery from a PHB fence event on POWER9. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-23phb4: Use phb4_ioda_sel() moreMichael Neuling1-7/+2
Use phb4_ioda_sel() in phb4_read_phb_status() rather than re-implementing it. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-23phb4: Improve config space loggingMichael Neuling1-7/+14
Log root complex accesses and print BFDN on device access Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-23phb4: Remove unused codeMichael Neuling1-10/+0
This is old unused code from phb3 so just remove it. No functional change Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-23phb4: Move code around to avoid indentingMichael Neuling1-53/+51
No functional change. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-23phb4: Update commentMichael Neuling1-1/+1
No functional change. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-23phb4: Reduce link degraded message log level to debugMichael Neuling1-1/+1
If we hit this message we'll retry and fix the problem. If we run out of retries and can't fix the problem, we'll still print a log message at error level indicating a problem. Signed-off-by: Michael Neuling <mikey@neuling.org> Reported-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-23phb4: Fix GEN3 for DD2.00Michael Neuling1-1/+1
In this fix: 62ac7631ae phb4: Fix PCIe GEN4 on DD2.1 and above We fixed DD2.1 GEN4 but broke DD2.00 as GEN3. This fixes DD2.00 back to GEN3. This time for sure! Signed-off-by: Michael Neuling <mikey@neuling.org> Tested-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com>
2017-10-18phb4: Fix PCIe GEN4 on DD2.1 and aboveMichael Neuling1-4/+3
In this change: eef0e197ab PHB4: Default to PCIe GEN3 on POWER9 DD2.00 We clamped DD2.00 parts to GEN3 but unfortunately this change also applies to DD2.1 and above. This fixes this to only apply to DD2.00. This also cleans up the documentation and printing. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-02phb4: Reassign link_retries counter in IODA purgeGuilherme G. Piccoli1-0/+2
Recently, a link_retries counter was added in pci/phb4 in order Skiboot can retry to train a link some times - default number of attempts to retrain a link is 3. Happens that, if during a regular boot process we exhaust the link retries and fail to train a PHB, the variable link_retries is stuck in 0. If a kdump happens later, a PHB reset procedure is triggered by Linux and, since we have a decrement-and-test in this variable, we end up setting it to -1; it's unsigned, hence we get an overflow. This patch fixes the issue by reassigning the default value to link_retries in every IODA purge. Signed-off-by: Guilherme G. Piccoli <gpiccoli@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-02phb4: Add additional adapter to retrain whitelistJohn W Walthour1-2/+3
The single port version of the ConnectX-5 has a different device ID 0x1017. Updated descriptions to match pciutils database. Signed-off-by: John Walthour <jwalthour@us.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-10-02phb4: make retry_whitelist staticStewart Smith1-1/+1
Silences sparse warning: hw/phb4.c:XX:20: warning: symbol 'retry_whitelist' was not declared. Should it be static? Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-28capi: Mask Psl Credit timeout error for P9Vaibhav Jain1-0/+4
Mask the PSL credit timeout error in CAPP FIR Mask register bit(46). As per the h/w team this error is now deprecated and shouldn't cause any fir-action for P9. Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Acked-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-27phb4: Update link training documentationMichael Neuling1-0/+8
We added degraded link retries in: 3f936bae97 phb4: Retrain link if degraded but forgot to update the documentation. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-27phb4: Additional RXE_ARB: DEC Stage Valid Error fixMichael Neuling1-3/+3
In this recent fix: 8b4c7a3cef phb4: Mask RXE_ARB: DEC Stage Valid Error We worked around a problem but the workaround wasn't complete. Now that we have full documentation and details on the issue, we have additional registers we need to change inits on. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-20capi: CAPP recoveryChristophe Lombard1-5/+54
CAPP recovery is initiated when a CAPP Machine Check is detected. The capp recovery procedure is initiated via a Hypervisor Maintenance interrupt (HMI). CAPP Machine Check may arise from either an error that results in a PHB freeze or from an internal CAPP error with CAPP checkstop FIR action. An error that causes a PHB freeze will result in the link down signal being asserted. The system continues running and the CAPP and PSL will be re-initialized. Tests performed on some of the old/new hardware. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-20phb4: Mask RXE_ARB: DEC Stage Valid ErrorMichael Neuling1-2/+2
Change the inits to mask out the RXE ARB: DEC Stage Valid Error (bit 370. This has been a fatal error but should be informational only. This update will be in the next version of the phb4 workbook. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-19PHB4: Default to PCIe GEN3 on POWER9 DD2.00Stewart Smith1-0/+6
You can use the NVRAM override for DD2.00 screened parts. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-15phb4: Use link if degradedMichael Neuling1-1/+7
In the recent change: 3f936bae97 phb4: Retrain link if degraded We retrain if the link is degraded. We do 3 retries to get an optimal link. Unfortunately if the last retry fails, we mark the PHB as bad and don't use it. Hence that PHB is lost even though it actually trained (just degraded). This fixes the problem by printing an error message (as below) but still marking the PHB as good. [ 7.179320404,3] PHB#0005[0:5]: LINK: Link degraded [ 8.387346665,3] PHB#0005[0:5]: LINK: Link degraded [ 10.078409137,3] PHB#0005[0:5]: LINK: Link degraded [ 11.281477269,3] PHB#0005[0:5]: LINK: Link degraded [ 11.283123885,3] PHB#0005[0:5]: LINK: Degraded but no more retries Signed-off-by: Michael Neuling <mikey@neuling.org> Acked-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12phb4: Retrain link if degradedMichael Neuling1-1/+133
On P9 Scale Out (Nimbus) DD2.0 and Scale in (Cumulus) DD1.0 (and below) the PCIe PHY can lockup causing training issues. This can cause a degradation in speed or width in ~5% of training cases (depending on the card). This is fixed in later chip revisions. This issue can also cause PCIe links to not train at all, but this case is already handled. This patch checks if the PCIe link has trained optimally and if not, does a full PHB reset (to fix the PHY lockup) and retrain. One complication is some devices are known to train degraded unless device specific configuration is performed. Because of this, we only retrain when the device is in a whitelist. All devices in the current whitelist have been testing on a P9DSU/Boston, ZZ and Witherspoon. We always gather information on the link and print it in the logs even if the card is not in the whitelist. For testing purposes, there's an nvram to retry all PCIe cards and all P9 chips when a degraded link is detected. The new option is 'pci-retry-all=true' which can be set using: nvram -p ibm,skiboot --update-config pci-retry-all=true This option may increase the boot time if used on a badly behaving card. Signed-off-by: Michael Neuling <mikey@neuling.org> [stewart@linux.vnet.ibm.com: fix Cumulus VERS_MAJ r.e. Mikey mail] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12phb4: Make link retries a #defineMichael Neuling1-1/+1
Make link retries a #define rather than open coding it in the PHB4 init code. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12phb4: Split phb4_get_link_state() into a new functionMichael Neuling1-6/+21
Split phb4_get_link_state() into a new function so that it can be reused to get info on the speed and width of the link. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12phb4: Move nvram read of pci-eeh-mmio initMichael Neuling1-1/+3
Move nvram read to the PHB4 init code so that's it's only read once, rather than every time we go though PHB reset. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-12phb4: Remove stable retriesMichael Neuling1-7/+0
This code was never used (since retries is set to 0), it's not very useful and it makes the code harder to read. So lets just remove it. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-05phb4: Fix bad whitespaceRussell Currey1-1/+1
Cc: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Russell Currey <ruscur@russell.cc> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-09-04capi: POWER9 DD2 updateChristophe Lombard1-64/+112
The CAPI initialization sequence has been updated in DD2. This patch adapts to the changes, retaining compatibility with DD1. The patch includes some changes to DD1 fix-ups as well. Tests performed on some of the old/new hardware. Some CAPP registers are initialized through the initfile p9.cxa.scom as the CAPP FIR, Transport Control and Snoop control registers. The following features will be added soon: - CAPP recovery. - Credit setup for Non Blocking Write + force quiesce. - Disable CAPI mode. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-11phb4: Enhanced PCIe training tracingMichael Neuling1-2/+46
This add more details to the PCI training tracing (aka Rick Mata mode). It enables the PCIe Link Training and Status State Machine (LTSSM) tracing and details on speed and link width. Output now looks like this when enabled (via nvram): [ 1.096995141,3] PHB#0000[0:0]: TRACE:0x0000001101000000 0ms GEN1:x16:detect [ 1.102849137,3] PHB#0000[0:0]: TRACE:0x0000102101000000 11ms presence GEN1:x16:polling [ 1.104341838,3] PHB#0000[0:0]: TRACE:0x0000182101000000 14ms training GEN1:x16:polling [ 1.104357444,3] PHB#0000[0:0]: TRACE:0x00001c5101000000 14ms training GEN1:x16:recovery [ 1.104580394,3] PHB#0000[0:0]: TRACE:0x00001c5103000000 14ms training GEN3:x16:recovery [ 1.123259359,3] PHB#0000[0:0]: TRACE:0x00001c5104000000 51ms training GEN4:x16:recovery [ 1.141737656,3] PHB#0000[0:0]: TRACE:0x0000144104000000 87ms presence GEN4:x16:L0 [ 1.141752318,3] PHB#0000[0:0]: TRACE:0x0000154904000000 87ms trained GEN4:x16:L0 [ 1.141757964,3] PHB#0000[0:0]: TRACE: Link trained. [ 1.096834019,3] PHB#0001[0:1]: TRACE:0x0000001101000000 0ms GEN1:x16:detect [ 1.105578525,3] PHB#0001[0:1]: TRACE:0x0000102101000000 17ms presence GEN1:x16:polling [ 1.112763075,3] PHB#0001[0:1]: TRACE:0x0000183101000000 31ms training GEN1:x16:config [ 1.112778956,3] PHB#0001[0:1]: TRACE:0x00001c5081000000 31ms training GEN1:x08:recovery [ 1.113002083,3] PHB#0001[0:1]: TRACE:0x00001c5083000000 31ms training GEN3:x08:recovery [ 1.114833873,3] PHB#0001[0:1]: TRACE:0x0000144083000000 35ms presence GEN3:x08:L0 [ 1.114848832,3] PHB#0001[0:1]: TRACE:0x0000154883000000 35ms trained GEN3:x08:L0 [ 1.114854650,3] PHB#0001[0:1]: TRACE: Link trained. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-11phb4: Fix reading wrong size registers in EEH dumpRussell Currey1-3/+3
These registers are supposed to be 16bit, and it makes part of the register dump misleading. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
generated by cgit v1.1 at 2024-10-11 07:09:44 +0000