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In p7ioc_err_inject_io32() addr is passed as an argument.
Based on its value , we have a conditional check(s).
Re-assigning the addr to 0x0ull, make the whole branching
check(s) a dead code.
Remove the re-assignment of addr, to fix the issue.
Fixes Coverity defect#101020.
Signed-off-by: Kamalesh Babulal <kamalesh@linux.vnet.ibm.com>
Cc: Gavin Shan <gwshan@linux.vnet.ibm.com>
Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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p7ioc_phb->{tve_hi_cache, tve_hi_cache} are array with upper bound
of 128. In p7ioc_map_pe_dma_window(), we check if the range is 1..255,
which might overrun the array.
Fix it by checking for array index not greater than 127.
Fixes Coverity Defect#97847.
Signed-off-by: Kamalesh Babulal <kamalesh@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Fix uninitialized variable warning in p7ioc_err_inject_io32().
Fixes Coverity defect #97880
Signed-off-by: Kamalesh Babulal <kamalesh@linux.vnet.ibm.com>
Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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The opal eeh interrupt handlers raise an opal event
(OPAL_EVENT_PCI_ERROR) whenever there is some processing required from
the OS. The OS then needs to call opal_pci_next_error(...) in a loop
passing each phb in turn to clear the event.
However opal_pci_next_error(...) clears the event unconditionally
meaning it would be possible for eeh events to be cleared without
processing them leading to missed events.
This patch fixes the problem by keeping track of eeh events on a
per-phb basis and only clearing the opal event once all phb eeh events
have been cleared.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Now that opal.h includes opal-api.h, there are a bunch of files that
include both but don't need to.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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In several places, a "bus/device/function" u16 was being directly
or'ed into an address using a left-shift. This should be using
SETFIELD, especially now that all _LSH have been removed.
Change use of BDFN (bus/device/function) field from using plain
left-shift to using SETFIELD(). Add proper BDFN field definitions.
Signed-off-by: Dan Streetman <ddstreet@ieee.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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The last two patches updated GETFIELD() and SETFIELD() to no longer
require the user to specify the mask and shift of a field, and to
remove all _LSH defines and rename any _MASK defines. There are
some places where the masks were used directly, where the caller
needs to have the _MASK suffix removed. There are also two users
of SETFIELD() where the field name still has the _MASK suffix
because there is an existing macro with the base name.
Change users of SETFIELD() to include the _MASK suffix where needed.
Change direct users of any mask to remove the _MASK suffix.
Signed-off-by: Dan Streetman <ddstreet@ieee.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This is probably not the best collection of things in the world,
but it means that opal.h is much closer to being directly usable
by an OS.
This triggers a bunch of #include fixes throughout the tree.
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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The patch refactors the code we had for PCI error injection. It
doesn't change the logic:
* Rename names of error types and functions according to the
comments given by Michael Ellerman when reviewing the kernel
counterpart.
* Split The backend of error injection for PHB3 and P7IOC to
multiple functions to improve code readability. Some logics
are simplified without affecting their original functionality.
* Misc cleanup like renaming variables and functions.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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The patch adds function pci_device_init(), which is called by
phb->ops->device_init() to apply common initialization on the
specified PCI device during bootup or after PE reset.
Currently, we only put the logic of MPS configuration to the
function, but more will be put there.
Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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The complete reset could be issued by kdump kernel to remove pending
PCI traffic in order to avoid EEH errors in kdump scenario. However,
the bus numbers configured into PCI bridges would be lost after the
reset and it would cause that some of PCI devices (e.g. IPR) can't
be probed by kdump kernel successfully.
The patch fixes above issue by restoring bus numbers after complete
reset. It's responsing to bug#113210
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Save stack space, remove code and improve logging all in one handy patch.
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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The patch introduces a new OPAL API opal_pci_eeh_freeze_set(),
which allows to set frozen state for the specified PE, so that
we can support "compound" PE in kernel.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Though the p7ioc spec states the errors triggered by PAPR error
injection register set (0x2b0, 0x2b8, 0x2c0) should be one-shot
without "sticky" bit, Firebird-L machine doesn't follow the rule.
It will cause endless frozen PE until we have to remove the PE
permanently.
The patch extends opal_pci_reset() allowing kernel to clear PAPR
error injection register set at appropriate point.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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The patch implements P7IOC backend to support error injection. There are
3 registers (control, address and mask) for each P7IOC PHB to do error
injection. The way to do error injection is straight-forward. For IO,
MMIO and PCI-CFG error injection, we check the address is valid or not.
The address will be used for error injection if that's valid. Otherwise,
we have to figure one out from IODT, M32DT or PELTM.
As DMA address is natually invisible to users, we just figure it out from
TVT and use that for error injection.
64-bits error injection will be supported later.
Signed-off-by: Mike Qiu <qiudayu@linux.vnet.ibm.com>
Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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We need apply errata based on PHB version in future. So lets grab
it at PHB initialization time.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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I can't quite figure what this code was trying to do, but
I don't see how it would help, phb3_read_phb_status() should
already have the right amount of locking in the caller.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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