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Add new device-tree property 'ops' to define different operations
supported on each sensor-group.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Adds a generic API to clear sensor groups. OCC inband sensor groups
such as CSM, Profiler and Job Scheduler can be cleared using this API.
It will clear the min/max of all sensors belonging to OCC sensor
groups.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Add support to set the CPU-GPU power shifting ratio which is used by
the OCC power capping algorithm. PSR value of 100 takes all power away
from CPU first and a PSR value of 0 caps GPU first.
Documentation enhanced by Stewart Smith.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This patch adds a generic powercap framework and exports OCC powercap
sensors using which system powercap can be set inband through OPAL-OCC
command-response interface.
Documentation for powercap enhanced by Stewart Smith.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This patch adds support for a shared memory based command/response
interface between OCC and OPAL. In HOMER, there is an OPAL command
buffer and an OCC response buffer which is used to send inband
commands to OCC.
The OPAL-OCC command/response sequence is as follows:
1. Check if both 'OCC Progress' bit in OCC response flag and 'Cmd Ready'
bit in OPAL command flag are set to zero. If yes then proceed with
below steps to send a command to OCC.
2. Write the command value, request ID and command specific data
to the OPAL command buffer.
3. Clear the response flag and set the 'Cmd Ready' bit in OPAL command
flag to indicate command is ready.
4. OCC will poll the command flag every 4ms to check if 'Cmd Ready' bit
is set by OPAL. If the bit is set then OCC will set the 'OCC Progress'
bit.
5. OCC will process the command and write the response to the OCC response
buffer and set the 'Rsp Ready' bit in the response flag and sends an
interrupt.
8. OPAL will receive the interrupt and queue the response to the host.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Reviewed-by: Cyril Bur <cyril.bur@au1.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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ulta_turbo_supported will always be true in this codepath,
so the condition isn't needed
found by static analysis
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Found by static analysis
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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When entering this section of code rc will be zero. If fsp_mkmsg() fails
the code responsible for printing an error message won't be set.
Resetting rc should allow for the error case to trigger if fsp_mkmsg
fails.
Fixes: 3c64f79ad2220d03a0af49d44f0548e08da54a44
Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com>
[stewart@linux.vnet.ibm.com: add Fixes]
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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In P9 FSP box, OCC image is pre-loaded. So do not handle the load
command and send SUCCESS to FSP on recieving OCC_LOAD mbox message.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This patch adds support to share the I2C engines with host and OCC.
OCC uses I2C engines to read DIMM temperatures and to communicate with
GPU. OCC Flag register is used for locking between host and OCC. Host
requests for the bus by setting a bit in OCC Flag register. OCC sends
an interrupt to indicate the change in ownership.
Originally-from: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
[stewart@linux.vnet.ibm.com: Pretty heavily rework logic, including
fixing bus owner change and separating out occ lock from sensor cache]
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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In P9, once OCC is up, it is supposed to setup the cores to nominal
frequency. So skip this step in OPAL.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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In P9 the pstate values are positive. They are continuous set of
unsigned integers [0 to +N] where Pmax is 0 and Pmin is N. The
linear ordering of pstates for P9 has changed compared to P8.
P8 has neagtive pstate values advertised as [0 to -N] where Pmax
is 0 and Pmin is -N. This patch adds helper routines to abstract
pstate comparison with pmax and adds sanity pstate limit checks.
This patch also fixes pstate arithmetic by using labs().
Suggested-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This patch fixes the SCOM address for OCC_MISC register which is used
for OCC interupts. In P9, OCC sends an interrupt to notify change in
the shared memory like throttle status. This patch handles this
interrupt reason.
Originally-from: Michael Neuling <mikey@neuling.org>
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
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Currently chip->occ_functional data field set's to true always whether
ibm,occ-functional-state property exists or not.
ibm,occ-functional-state property of xscom node's are populated only in
ibm,fsp systems by detecting the OCC state in OPAL/SPIRA. In
non-fsp(i.e OpenPower) systems this property is not populating. But OPAL
sets chip->occ_functional field incorrectly to true without acually knowing
the occ state.
OCC Spec says:
When OCC is told to go active it will populate OCC-OPAL shared memory
interface with ‘valid’ and all Pstate data.
So incase of OpenPower systems OPAL can add DT property
ibm,occ-functional-state and set the chip->occ_functional when OPAL finds
the valid homer region and corresponding occ_valid byte is set to 0x1.
Signed-off-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com>
[stewart@linux.vnet.ibm.com: squash commits, tweak commit message]
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This is an experimental patch that implements "Fast reboot" on P8
machines.
The basic idea is that when the OS calls OPAL reboot, we gather all
the threads in the system using a combination of patching the reset
vector and soft-resetting them, then cleanup a few bits of hardware
(we do re-probe PCIe for example), and reload & restart the bootloader.
For Trusted Boot, this means we *add* measurements to the TPM, so you
will get *different* PCR values as compared to a full IPL. This makes
sense as if you want to be sure you are running something known then,
well, do a full IPL as soft reset should never be trusted to clear any
malicious code.
This is very experimental and needs a lot of testing and also auditing
code for other bits of HW that might need to be cleaned up.
BenH TODO: I also need to check if we are properly PERST'ing PCI devices.
This is partially based on old code I had to do that on P7. I only
support it on P8 though as there are issues with the PSI interrupts
on P7 that cannot be reliably solved.
Even though this should be considered somewhat experimental, we've had
a lot of success on a variety of machines. Dozens/hundreds of reboots
across Tuleta, Garrison and Habanero.
Currently, we've hidden it behind a NVRAM config option, which *is*
liable to change in the future (to ensure that only those who know
what they're doing enable it)
You can enable the experimental support via nvram option:
nvram -p ibm,skiboot --update-config experimental-fast-reset=feeling-lucky
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[stewart@linux.vnet.ibm.com: hide behind nvram option, include Mambo fixes
from Mikey]
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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During an OCC reset cycle the system is forced to Psafe pstate.
When OCC becomes active, the system has to be restored to its
last pstate as requested by host. So host needs to be notified
of OCC_RESET event or else system will continue to remian in
Psafe state until host requests a new pstate after the OCC
reset cycle.
This patch defines 'OPAL_PRD_MSG_TYPE_OCC_RESET_NOTIFY' to
notify OPAL when opal-prd issues OCC reset. OPAL will queue
OCC_RESET message to host when it receives opal_prd_msg of
type '*_OCC_RESET_NOTIFY'.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
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Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Be a bit clearer in the impact of some of these errors.
Suggested-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This lets us use FWTS to check that we haven't errored out enabling
OCCs, which is a (relatively) common error that crops up and since
we continue to boot without OCCs, things still work fine, it's just
we don't get any power or frequency scaling.
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Parse the entire pstate table provided by OCC and filter out the
entries that are outside the Pmax and Pmin limits. This can
occur when turbo mode is disabled and OCC limits the Pmax to
nominal pstate, but includes turbo pstates in the pstate table.
We end up with wrong pstates in such cases if we do not parse
the pstate table to filter out the correct range.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Acked-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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When constructing the pstate entries in the device tree we allocate
MAX_PSTATES, even though we know that there are nr_pstates.
Use this information to allocate nr_pstates and potentially save us some
heap.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Acked-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Add support to read OCC-OPAL shared memory region version2 to parse
ultra-turbo pstates and core-to-max-pstate-allowed array and append
it to device tree. Each element of core-to-max-pstate-allowed indicates
the maximum pstate sustained with 'n' online cores.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Fixes: a804c1b2c13f
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Modify the OCC reset order such that master OCC is reset after the
slave OCCs are reset. In Tuleta/Alpine systems 'proc0' will always be
the master OCC, which has to be stopped last when FSP sends OCC_RESET
command to Opal.
This fixes BZ 119718, SW289036
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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hw/occ.c:278:2: warning: Value stored to 'rc' is never read
rc = xscom_read(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_PPMCR), &tmp);
^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
hw/occ.c:309:2: warning: Value stored to 'rc' is never read
rc = xscom_read(chip->id, XSCOM_ADDR_P8_EX_SLAVE(core, EX_PM_PPMSR), &tmp);
^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Since skiboot is all BE, this doesn't make a difference in code generated.
It does silence the following sparse warnings though:
hw/occ.c:354:38: warning: incorrect type in assignment (different base types)
hw/occ.c:354:38: expected restricted beint64_t [usertype] type
hw/occ.c:354:38: got int
hw/occ.c:370:46: warning: incorrect type in assignment (different base types)
hw/occ.c:370:46: expected restricted beint64_t [addressable] [assigned] [usertype] type
hw/occ.c:370:46: got int
hw/occ.c:371:46: warning: incorrect type in assignment (different base types)
hw/occ.c:371:46: expected restricted beint64_t [addressable] [assigned] [usertype] chip
hw/occ.c:371:46: got unsigned int [unsigned] [usertype] id
hw/occ.c:372:57: warning: incorrect type in assignment (different base types)
hw/occ.c:372:57: expected restricted beint64_t [addressable] [assigned] [usertype] throttle_status
hw/occ.c:372:57: got unsigned char [unsigned] [usertype] throttle
hw/occ.c:477:49: warning: incorrect type in initializer (different base types)
hw/occ.c:477:49: expected restricted beint64_t [usertype] type
hw/occ.c:477:49: got int
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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In some simulation environments, we simulate a system close to an
ibm-fsp system but with a crucial difference: we don't simulate OCCs.
This means that for a P8 (well, a simulated one) that looks like it's
part of a ibm-fsp system, we'd wait around for about a minute to be
asked to start OCCs and for the OCCs to start. Obviously, this would
never happen and we'd hit the OCC initialization timeout (correctly)
logging an error.
However, in this simulation environment, it isn't an error as the
required information to work out it isn't an error is (at least now)
provided in hdat under 'OCC Functional State'.
Previously, the ibm,occ-functional-state property was just passed
through the device tree to the host through the XSCOM node and
skiboot ignored it.
This patch takes note of occ-functional-state and skips waiting for
OCCs on any chips that have been marked as having non functional
OCC.
In such simulation environments this means we:
a) don't log an error that isn't really an error
b) boot 1 minute quicker as we don't hit the timeout.
Tested-by: Gajendra B Bandhu1 <gbandhu1@in.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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In the event of a lot of OCC events (or many CPU cores), we could
send many OCC messages to the host, which if it wasn't calling
opal_get_msg really often, would cause skiboot to malloc() additional
messages until we ran out of skiboot heap and things didn't end up
being much fun.
When running certain hardware exercisers, they seem to steal all time
from Linux being able to call opal_get_msg, causing these to queue up
and get "opalmsg: No available node in the free list, allocating" warnings
followed by tonnes of backtraces of failing memory allocations.
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Recent HostBoot & SBE firmware provide a HW timer facility that can
be used to implement OPAL timers and thus limit the reliance on the
Linux heartbeat.
This implements support for it. The side effect is that i2c from Centaurs
is now usable.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[stewart@linux.vnet.ibm.com: fix run-timer unit test]
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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There are now no users of the call_out parameter and future users should
use the log_append_msg() and log_append_data() functions, so remove all
references to call_out.
Signed-off-by: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com>
Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Add a new class of message definition OPAL_MSG_OCC to
opal_message_type to notify the following OCC events to host:
1) OCC Reset
2) OCC Load
3) OCC Throttle Status Change
Add an opal poller to periodically read throttle status updated by OCC
for each chip and notify any change in throttle status to host. The
throttle status indicates the reason why OCC may have limited the max
Pstate of the chip.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Reviewed-by: Preeti U Murthy <preeti@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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We were previously asking the OCC of the current chip to generate
the self interrupt. If Hostboot does not configure all the PSI Host
Bridges, so if the current chip happens to have an unconfigured PSI HB,
the chip will never see the interrupt.
Instead grab a chip id from the list of configured PSIs, and ask the OCC
on that chip to generate the self-interrupt.
This adds a pointer to the chip's PSI in struct proc_chip so we can
use the current chip's PSI if it is active without having to look
through all of them.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
cc: Neelesh Gupta <neelegup@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Commit 4db0c1e4f introduced occ_load_req queue. With that changes we queue
the occ load request if hostservice LID load is not complete. And we have
callback function (occ_poke_load_queue)...which takes care of calling
__occ_do_load().
But current code proceeds and calls __occ_do_load() after queueing....which
is not correct. So just return if we queue the occ load request.
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
Acked-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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We need to pass the PNOR access status to the OCCs, as they may write to
the PNOR in the event of a checkstop.
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
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This change hooks the OCC TMGT interrupt path into the PRD's
prd_tmgt_interrupt function.
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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There is no guarantee that a hostservices lid load request will arrive
after we have cached the required lids. For such cases, queue the
request and service them after caching.
Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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And add some basic qemu quirks
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Currently, the occ_interrupt handler will clear the interrupt bit along
with the interrupt reason. If an irq has occurred between the read and
the clear, we'll mask out interrupt bit for that new event
This change checks the reason bits after clearing the interrupt bit. If
any are set, we re-set the interrupt bit to trigger another interrupt.
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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The OCC interrupt register only exists on P8, accessing it on P7 causes
not only error logs but also causes PRD to eventually gard chips.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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During characterisation, we'd like to allow userspace to see the vdd and
vcs values exposed by the OCC. This change adds two new properties to
expose these:
ibm,pstate-vdds
ibm,pstate-vcss
- containing one byte per pstate, representing the Vdd or Vcs value for
that pstate.
Becuase we now have a few different error paths (one for each allocation
failure), we consolidate the free()s into a single path.
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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If the OCC interrupt comes from another chip, we incorrectly try to clear
it on the local one. This causes hangs at boot on some machines.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Commit cf6f4e8912d29fb89ce85c84834607065ad595a5 introduced a platform
independent frontend for error logging. However it failed to move the
generic parts of the fsp-elog.h header into the platform independent
one, instead relying on the fact that up until now fsp-elog.h was
included whenever a function needed to log errors.
This patch moves the platform independent defines into the frontend
header file (errorlog.h) and removes the include of the platform
specific header in generic code paths.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Mambo doesn't implement various things such as PBA SCOMs, LPC,
ChipTOD, etc... It also provides a special console hook.
This adds detection of Mambo via the /mambo node, and enables
us to boot all the way to Linux.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This function uses int arrays from stack that pushes stack usage to
more than 2kB. Reduce stack usage by allocating memory.
Ben H's stack check compile option exposed this usage count:
hw/occ.c: In function 'add_cpu_pstate_properties':
hw/occ.c:187:1: warning: the frame size of 2064 bytes is larger than
2048 bytes [-Wframe-larger-than=]
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Modify the FSP response message to include the status code in the
status/error byte instead of adding a new word to it which is
incorrect.
FSP ack messages are 2 words with status in the 3rd byte of second
word. Status byte is in the extra (3rd) word only on new status
messages from OPAL to FSP.
Code corrected based on FSP mailbox spec version 3.16.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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OPAL is expected to leave OCC stopped after receiving reset OCC
message from FSP. FSP will send this either at boot before
a load/start, or during runtime before load/start. If there
is no subsequent load/start command, the OCC can be left stopped.
After few attempts (runtime reset), FSP can just send reset and
expect OPAL to leave OCC in stopped state.
Call HBRT to stop OCC on FSP reset OCC command and acknowledge.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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