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Currently, the occ_interrupt handler will clear the interrupt bit along
with the interrupt reason. If an irq has occurred between the read and
the clear, we'll mask out interrupt bit for that new event
This change checks the reason bits after clearing the interrupt bit. If
any are set, we re-set the interrupt bit to trigger another interrupt.
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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The OCC interrupt register only exists on P8, accessing it on P7 causes
not only error logs but also causes PRD to eventually gard chips.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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During characterisation, we'd like to allow userspace to see the vdd and
vcs values exposed by the OCC. This change adds two new properties to
expose these:
ibm,pstate-vdds
ibm,pstate-vcss
- containing one byte per pstate, representing the Vdd or Vcs value for
that pstate.
Becuase we now have a few different error paths (one for each allocation
failure), we consolidate the free()s into a single path.
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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If the OCC interrupt comes from another chip, we incorrectly try to clear
it on the local one. This causes hangs at boot on some machines.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Commit cf6f4e8912d29fb89ce85c84834607065ad595a5 introduced a platform
independent frontend for error logging. However it failed to move the
generic parts of the fsp-elog.h header into the platform independent
one, instead relying on the fact that up until now fsp-elog.h was
included whenever a function needed to log errors.
This patch moves the platform independent defines into the frontend
header file (errorlog.h) and removes the include of the platform
specific header in generic code paths.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Mambo doesn't implement various things such as PBA SCOMs, LPC,
ChipTOD, etc... It also provides a special console hook.
This adds detection of Mambo via the /mambo node, and enables
us to boot all the way to Linux.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This function uses int arrays from stack that pushes stack usage to
more than 2kB. Reduce stack usage by allocating memory.
Ben H's stack check compile option exposed this usage count:
hw/occ.c: In function 'add_cpu_pstate_properties':
hw/occ.c:187:1: warning: the frame size of 2064 bytes is larger than
2048 bytes [-Wframe-larger-than=]
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Modify the FSP response message to include the status code in the
status/error byte instead of adding a new word to it which is
incorrect.
FSP ack messages are 2 words with status in the 3rd byte of second
word. Status byte is in the extra (3rd) word only on new status
messages from OPAL to FSP.
Code corrected based on FSP mailbox spec version 3.16.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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OPAL is expected to leave OCC stopped after receiving reset OCC
message from FSP. FSP will send this either at boot before
a load/start, or during runtime before load/start. If there
is no subsequent load/start command, the OCC can be left stopped.
After few attempts (runtime reset), FSP can just send reset and
expect OPAL to leave OCC in stopped state.
Call HBRT to stop OCC on FSP reset OCC command and acknowledge.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This makes OPAL use the OCC interrupt facility to send itself an interrupt
whenever the OPAL event bit is set as a result of an OPAL call that wasn't
itself opal_handle_interrupt() or opal_handle_hmi() (both of which we know
the OS will already deal with appropriately).
This ensures that OPAL event changes are notified to Linux via its
interrupt path which is necessary for it to properly broadcast the state
change to its various clients.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Basically, errors should be logged as errors and for the most part,
standard booting with log level of PR_NOTICE doesn't need debug
level output.
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Presently we are logging informational event if OCC timeout happens
during boot. Change the severity to Unrecoverable Error.
Also updated the elog description.
Sample Output:
|------------------------------------------------------------------------------|
| Entry Id Commit Time SubSystem Committed by |
| Platform Id State Event Severity Ascii Str |
|------------------------------------------------------------------------------|
| 0x53A530C8 10/09/2014 10:13:06 CEC Hardware Subsystem OC |
| 0xB0000001 Sent to Hypervisor Unrecoverable Error BB82C013 |
|------------------------------------------------------------------------------|
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Acked-by: Deepthi Dharwar <deepthi@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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When the fast/deep power management modes for the cpu idle states
is initialized, bits which are not relevant in this context are also
being set. Fix this.
Besides this, the EX_PM_GP1 register will be read/written into by the
OCC as well. We touch this register during initialization of fast/deep
cpuidle modes and during initialization of pstate transitions. The register
contents can thus get messed up due to potential race conditions between
the OCC and sapphire settings.
Hence make use of the AND and OR scoms to do the settings and hence
let the hardware take care of the necessary synchronization.
We can also get rid of the setting of deep mode during slw_reinit since
we enable the required deep winkle mode during slw_init itself. This means
effectively removing the slw_prepare_chip() and its children functions.
They are no longer useful.
Signed-off-by: Preeti U Murthy <preeti@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Keep it 0 for open-power platforms where OCC is going to be preloaded,
also avoids a annoying 1mn delay on early openpower and bml when there
is no OCC firmware to wait for.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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OCC F/w team recommends 60s timeout waiting for OCC to init. OCC has
to wait for memory throttle calibration from hardware procedure and
that takes 10s of seconds on large memory configurations. In one of
the failing case, it took 24s for OCC to init.
Typically OCC takes 2-5 secs to boot and we do that in parallel with
skiboot inits. But on certain corner cases with large memory,
we have to wait for 60s before we give up.
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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