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Power 9 introduces NX gzip compression engine. This patch adds gzip
compression support in NX. Virtual Accelerator Switch (VAS) is used to
access NX gzip engine and the channel configuration will be done with
the receive FIFO. So RxFIFO address, logical partition ID (lpid),
process ID (pid) and thread ID (tid) are used to configure RxFIFO.
P9 NX supports high and normal priority FIFOS. Skiboot configures User
Mode Access Control (UMAC) noitify match register with these values and
also enables other registers to enable / disable the engine.
Creates the following device-tree entries to provide RxFIFO address,
RxFIFO size, Fifo priority, lpid, pid and tid values so that kernel
can drive P9 NX gzip engine.
The following nodes are located under an xscom node:
/xscom@<xscom_addr>/nx@<nx_addr>
/ibm,gzip-high-fifo : High priority gzip RxFIFO
/ibm,gzip-normal-fifo : Normal priority gzip RxFIFO
Each RxFIFO node contains:
compatible : ibm,p9-nx-gzip
priority : High or Normal
rx-fifo-address : RxFIFO address
rx-fifo-size : RxFIFO size
lpid : 0xfff (1's for 12 bits in UMAC notify match
register)
pid : gzip coprocessor type
tid : counter for gzip
Signed-off-by: Haren Myneni <haren@us.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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P9 NX also supports gzip compression. So this patch creates
nx-compress.c and reorg nx-842.c code so that common functions that are
needed for both 842 and gzip compression will be moved in to
nx-compress.c. This patch does not change the actual functionality.
Signed-off-by: Haren Myneni <hmyneni@us.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Add support to parse and export OCC inband sensors which are copied
by OCC to main memory in P9. Each OCC writes three buffers which
includes one names buffer for sensor meta data and two buffers for
sensor readings. While OCC writes to one buffer the sensor values
can be read from the other buffer. The sensors are updated every
100ms.
This patch adds power, temperature, current and voltage sensors to
/ibm,opal/sensors device-tree node which can be exported by the
ibmpowernv-hwmon driver in Linux.
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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IMC (In Memory Collection) catalog is a repository of information
about the Performance Monitoring Units (PMUs) and their events under
the IMC infrastructure. The information include :
- The PMU names
- Event names
- Event description
- Event offsets
- Event scale
- Event unit
The catalog is provided as a flattened device tree (dtb). Processors
with different PVR values may have different PMU or event names. Hence,
for each processor, there can be multiple device tree binaries (dtbs)
containing the IMC information. Each of the dtb is compressed and forms
a sub-partition inside the PNOR partition "IMA_CATALOG". Here is a link
to the commit adding this partition to PNOR :
https://github.com/open-power/pnor/commit/c940142c6dc64dd176096dc648f433c889919e84
So, each compressed dtb forms a sub-partition inside the IMC pnor
partition and can be accessed/loaded through a sub-partition id which
is nothing but the PVR id. Based on the current processor's PVR, the
appropriate sub-partion will be loaded.
Note however, that the catalog information is in the form of a dtb and
the dtb is compressed too. So, the sub-partition loaded must be
decompressed first before we can actually use it.
It is important to mention here that while a PNOR image built for one
processor is specific to only that processor and isn't portable, a
single system generation (Processor version) may have multiple revisions
and these revisions may have some changes in their IMC PMUs and events,
and hence, the need for multiple IMC DTBs.
The sub-partition that we obtain from the IMC pnor partition is a
compressed device tree binary. We uncompress it using the libxz's
functions. After uncompressing it, we link the device tree binary to the
system's device tree. The kernel can now access the device tree and get
the IMC PMUs and their events' information.
Not all the IMC PMUs listed in the device tree may be available. This is
indicated by imc availability vector (which is a part of the IMC control
block structure). We need to check this vector and make sure to remove
the IMC device nodes which are unavailable.
Signed-off-by: Hemant Kumar <hemant@linux.vnet.ibm.com>
Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
[stewart@linux.vnet.ibm.com: use pr_fmt, fix failure path for resource load]
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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CAPP microcode flash download and CAPP upload for PHB4.
A new file 'capp.c' is created to receive common capp code for PHB3 and
PHB4.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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SBE sends passthrough command. We have to capture this interrupt and
send event to HBRT via opal-prd (user space daemon).
This patch adds minimal SBE code to capture SBE interrupt and send
event to opal-prd. Next patch will add opal-prd (user space) support.
CC: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This adds a global map for allocating physical memory address. This
centralises physical memory space allocations into one location rather
than spread through, PHB, XIVE, NX etc.
This adds a new call phys_map_get() which takes a chip, type and index
and returns a address and size for the region to be used.
An error in a call to this function crashes skiboot. This is done
since bogus calls here are going to be hit by developers not users and
they need to be fixed.
Currently only P9 is implemented but other chips should be easy to
add. On P9 BARs are generally set by skiboot. On P8 this was done by
hostboot so this is not needed there.
This just adds the infrastructure. User (PHB4, XIVE etc) will be
migrated in subsequent patches.
Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Unlike other system buses the NVLink2 links need to be trained at
runtime as training requires interaction from the GPU device
drivers. This patch implements the required training procedures for
NVLink2, which are different than the NVLink1 equivalents.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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NVLink2 is a new feature introduced on POWER9 systems. It is an
evolution of of the NVLink1 feature included in POWER8+ systems but
adds several new features including support for GPU address
translation using the Nest MMU and cache coherence.
Similar to NVLink1 the functionality is exposed to the OS as a series
of virtual PCIe devices. However the actual hardware interfaces are
significantly different which limits the amount of common code that
can be shared between implementations in the firmware.
This patch adds basic hardware initialisation and exposure of the
virtual NVLink2 PCIe devices to the running OS.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This adds an internal skiboot API for accessing the AST BMC mbox
registers.
Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Implement a fake NVRAM device based on arbitrary memory reserves.
This allows NVRAM images to be preloaded without the FSP.
Signed-off-by: Jack Miller <jack@codezen.org>
Tested-by: Chris Smart <chris@distroguy.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This adds the base support for the PHB4. It currently only support
the M32 window, EEH or in general error recovery aren't supported
yet.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[stewart@linux.vnet.ibm.com: update (C) year, fix indenting]
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This provides basic initialization of the XIVE along with some OPAL calls
to emulate an old-style XICS which will initially be used by Linux for
backward compatibility.
The current implementation is limited to one priority and doesn't expose
much to Linux for future exploitation mode yet.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[stewart@linux.vnet.ibm.com: add (C) header, fix whitespace, missing breaks]
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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p5ioc2 is used by approximately 2 machines in the world, and has never
ever been a supported configuration.
Not only is the code virtually unused and very tricky to test, but
keeping it around is making life unnecessarily difficult:
- It's more complexity to manage for things such as PCI slot support
- It's more code for static analysis to cover, which means more time
fixing bugs that affect no-one.
- It's bloating every single install of skiboot for no benefit.
- It's reducing coverage stats, which is sad.
Drop p5ioc2.
Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This patch adds support for the NPU Nvlink PHB type. It provides
access to each nvlink in the system by exposing them as PCIe devices
under a NPU PHB type. Each PCIe device has a configuration space
implemented in software which indicates the base address of the
DL/TL/PL registers required by the device drivers.
It also presents one LSI per device which is used to signal device
drivers of changes in device status. The configuration space also adds
a vendor specific capability which is used primarily by device drivers
to power on an train the IBM PHY.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This adds a driver for standard CMOS RTC chips and use it from
the QEMU platform.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This patch adds a new sensor family for Digital Temperature Sensors
and a new resource class to capture the core temperatures.
Each core has four DTS located in different zones (LSU, ISU, FXU, L3).
The max of the four temperatures is computed and returned for the core
as well as a global trip point value. This is based on the meltbox tool.
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This change adds Processor Recovery Diagnostics (PRD) code to skiboot
firmware. This allows certain hardware RAS events to be handled by a
userspace application.
The core of the PRD code is a messaging interface to the kernel (and
onwards to userspace). PRD events are logged with the prd.c code, and
sent to the kernel as opal_msg messages. For responses to these
messages, the kernel will reply using a new OPAL call, opal_prd_msg.
Only one message is outstanding at a time; we collect events from
hardware interrupts (hooked up by subsequent patches), and set
per-processor event bits. Once an event has been consumed by the
kernel, we clear that event from out pending set, and send any further
pending events.
Certain events (hardware attentions from the psi layer) need to be
masked at interrupt time. For these, we have an acknowledgement facility
to clear the mask once the userspace PRD application has cleared the
source of the error.
Includes multiple contributions from:
Neelesh Gupta <neelegup@linux.vnet.ibm.com>
Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Neelesh Gupta <neelegup@linux.vnet.ibm.com>
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Add support for the 842 hw memory compression engine in the NX Coprocessor.
This moves the existing RNG support into its own nx-rng.c file, adds 842
support in a nx-842.c file, and creates a nx-crypto.c file to configure and
disable the crypto engines (which are not supported yet).
New nodes are created for each 842 engine found. This does not actually
process any of the data or drive the 842 engines, it only configures
registers to set up and enable/disable the engines appropriately, and
creates new nodes so the OS can drive the 842 engines.
Signed-off-by: Dan Streetman <ddstreet@ieee.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This patch adds the generic i2c driver infrastructure to handle multiple i2c
master cores present in the system and exposes structures and interfaces for
the client to perform I/O on the i2c slave devices.
The driver adds the capability to queue multiple requests from client and
let clients notified asynchronously after completion. It does that by
handling the i2c interrupt or through OPAL poller in the absence of
interrupt.
Signed-off-by: Neelesh Gupta <neelegup@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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The initial implementation of the ipmi stack was still tightly coupled
with the backend (in this case bt). This patch refactors the ipmi code
to use a generic backend device.
The core ipmi messaging functionality and the implementation of
specific commands has also been split into different files.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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This patch adds a basic IPMI layer to the sapphire core and support
for a BT IPMI interface as found on the Aspeed BMC of the Palmetto
platform
[ Changed the compatible property -- BenH ]
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Adds a fake RTC that can be initialized via a named reserve in the
device tree that may, at some point, be on NVRAM.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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