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2019-07-26hw: Introduce npu3Reza Arbab1-1/+1
POWER9P systems have been upgraded with NVLink 3.0 interconnects. The underlying hardware is fundamentally different--each POWER9 chip has (1 NPU) * (3 stacks) * (2 bricks) = (6 links) Where in each POWER9P chip, there are (3 NPUs) * (4 bricks) = (12 links) This flatter hierarchy simplifies the firmware implementation a bit, but also prevents sharing much common code with npu2. As in previous versions, initialize the hardware and expose each link to the OS as a virtual PCIe device. This initial support covers NVLink devices only, with OpenCAPI to follow. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26npu2: Refactor NPU OPAL callsReza Arbab1-0/+1
Abstract the OPAL entry points for npu2, moving them to a new file. This prepares us to add parallel npu3 versions of the same APIs. No functional change. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26npu2: Prepare purge_l2_l3_caches() for reuseReza Arbab1-1/+1
Move this to a separate compilation unit with its own header, for reuse. The code formerly in npu2.c is copied verbatim. The #defines formerly in npu2-regs.h have been reformatted and changed to use PPC_BITMASK() instead of multiple consecutive PPC_BIT()s. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26Dedup $(HW_OBJS)Reza Arbab1-4/+2
How did I notice one dup in aa56d9a2abdb ("Remove duplicate npu-common.o from $(HW_OBJS)"), but not the other five? Remove them too. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-19Move ec/ code to Rhesus platformStewart Smith1-1/+0
The embedded controller that Rhesus uses is exclusive to that platform, make it purely part of tha platform Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-06-04Remove P7 remnants: hw/cec.c, apollo platformStewart Smith1-1/+1
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-06-04Remove POWER7 and POWER7+ supportStewart Smith1-2/+1
It's been a good long while since either OPAL POWER7 user touched a machine, and even longer since they'd have been okay using an old version rather than tracking master. There's also been no testing of OPAL on POWER7 systems for an awfully long time, so it's pretty safe to assume that it's very much bitrotted. It also saves a whole 14kb of xz compressed payload space. Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Enthusiasticly-Acked-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-05-15Add P9 DIO interrupt supportLei YU1-1/+1
On P9 there are GPIO port 0, 1, 2 for GPIO interrupt, and DIO interrupt is used to handle the interrupts. Add support to the DIO interrupts: 1. Add dio_interrupt_register(chip, port, callback) to register the interrupt; 2. Add dio_interrupt_deregister(chip, port, callback) to deregister; 3. When interrupt on the port occurs, callback is invoked, and the interrupt status is cleared. Signed-off-by: Lei YU <mine260309@gmail.com> [oliver: Fixed Makefile.inc merge conflict] Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-05-02Write boot progress to LPC port 80hStewart Smith1-0/+1
This is an adaptation of what we currently do for op_display() on FSP machines, inventing an encoding for what we can write into the single byte at LPC port 80h. Port 80h is often used on x86 systems to indicate boot progress/status and dates back a decent amount of time. Since a byte isn't exactly very expressive for everything that can go on (and wrong) during boot, it's all about compromise. Some systems (such as Zaius/Barreleye G2) have a physical dual 7 segment display that display these codes. So far, this has only been driven by hostboot (see hostboot commit 90ec2e65314c). Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-01-16Remove duplicate npu2-common.o from $(HW_OBJS)Reza Arbab1-1/+1
We've listed npu2-common.o twice. Remove one. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-07-26hw/phb4: Fix unused value/parameter warningsAndrew Donnellan1-3/+0
Remove the phb4.c-specific CFLAGS that disable the unused value and unused parameter warnings, and cleanup the ensuing warnings. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-04-30Move P8 timer code to separate fileVasant Hegde1-1/+1
Lets move P8 timer support code from slw.c to sbe-p8.c (as suggested by BenH). There is a difference between timer support in P8 and P9. Hence I think it makes sense to name it as sbe-p8.c. Note that this is pure code movement and renaming functions/variables. No functionality changes. Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-03-01npu2-opencapi: Configure NPU for OpenCAPIAndrew Donnellan1-0/+2
Scan the device tree for NPUs with OpenCAPI links and configure the NPU per the initialisation sequence in the NPU OpenCAPI workbook. Training of individual links and setup of per-AFU/link configuration will be in a later patch. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-03-01npu2: Split out common helper functions into separate fileAndrew Donnellan1-1/+1
Split out common helper functions for NPU register access into a separate file, as these will be used extensively by both NVLink and OpenCAPI code. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Acked-by: Reza Arbab <arbab@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-02-28build: use thin archives rather than incremental linkingNicholas Piggin1-1/+1
This changes to build system to use thin archives rather than incremental linking for built-in.o, similar to recent change to Linux. built-in.o is renamed to built-in.a, and is created as a thin archive with no index, for speed and size. All built-in.a are aggregated into a skiboot.tmp.a which is a thin archive built with an index, making it suitable or linking. This is input into the final link. The advantags of build size and linker code placement flexibility are not as great with skiboot as a bigger project like Linux, but it's a conceptually better way to build, and is more compatible with link time optimisation in toolchains which might be interesting for skiboot particularly for size reductions. Size of build tree before this patch is 34.4MB, afterwards 23.1MB. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-22vas: Move core/vas.c -> hw/vas.cMichael Neuling1-1/+1
It's hardware after all... Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01NX: Add P9 NX support for gzip compression engineHaren Myneni1-1/+1
Power 9 introduces NX gzip compression engine. This patch adds gzip compression support in NX. Virtual Accelerator Switch (VAS) is used to access NX gzip engine and the channel configuration will be done with the receive FIFO. So RxFIFO address, logical partition ID (lpid), process ID (pid) and thread ID (tid) are used to configure RxFIFO. P9 NX supports high and normal priority FIFOS. Skiboot configures User Mode Access Control (UMAC) noitify match register with these values and also enables other registers to enable / disable the engine. Creates the following device-tree entries to provide RxFIFO address, RxFIFO size, Fifo priority, lpid, pid and tid values so that kernel can drive P9 NX gzip engine. The following nodes are located under an xscom node: /xscom@<xscom_addr>/nx@<nx_addr> /ibm,gzip-high-fifo : High priority gzip RxFIFO /ibm,gzip-normal-fifo : Normal priority gzip RxFIFO Each RxFIFO node contains: compatible : ibm,p9-nx-gzip priority : High or Normal rx-fifo-address : RxFIFO address rx-fifo-size : RxFIFO size lpid : 0xfff (1's for 12 bits in UMAC notify match register) pid : gzip coprocessor type tid : counter for gzip Signed-off-by: Haren Myneni <haren@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01NX: Organize NX compression code to include 842 and gzip supportHaren Myneni1-1/+1
P9 NX also supports gzip compression. So this patch creates nx-compress.c and reorg nx-842.c code so that common functions that are needed for both 842 and gzip compression will be moved in to nx-compress.c. This patch does not change the actual functionality. Signed-off-by: Haren Myneni <hmyneni@us.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-07-28sensors: occ: Add support for OCC inband sensorsShilpasri G Bhat1-1/+1
Add support to parse and export OCC inband sensors which are copied by OCC to main memory in P9. Each OCC writes three buffers which includes one names buffer for sensor meta data and two buffers for sensor readings. While OCC writes to one buffer the sensor values can be read from the other buffer. The sensors are updated every 100ms. This patch adds power, temperature, current and voltage sensors to /ibm,opal/sensors device-tree node which can be exported by the ibmpowernv-hwmon driver in Linux. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-27skiboot: Find the IMC DTBMadhavan Srinivasan1-1/+1
IMC (In Memory Collection) catalog is a repository of information about the Performance Monitoring Units (PMUs) and their events under the IMC infrastructure. The information include : - The PMU names - Event names - Event description - Event offsets - Event scale - Event unit The catalog is provided as a flattened device tree (dtb). Processors with different PVR values may have different PMU or event names. Hence, for each processor, there can be multiple device tree binaries (dtbs) containing the IMC information. Each of the dtb is compressed and forms a sub-partition inside the PNOR partition "IMA_CATALOG". Here is a link to the commit adding this partition to PNOR : https://github.com/open-power/pnor/commit/c940142c6dc64dd176096dc648f433c889919e84 So, each compressed dtb forms a sub-partition inside the IMC pnor partition and can be accessed/loaded through a sub-partition id which is nothing but the PVR id. Based on the current processor's PVR, the appropriate sub-partion will be loaded. Note however, that the catalog information is in the form of a dtb and the dtb is compressed too. So, the sub-partition loaded must be decompressed first before we can actually use it. It is important to mention here that while a PNOR image built for one processor is specific to only that processor and isn't portable, a single system generation (Processor version) may have multiple revisions and these revisions may have some changes in their IMC PMUs and events, and hence, the need for multiple IMC DTBs. The sub-partition that we obtain from the IMC pnor partition is a compressed device tree binary. We uncompress it using the libxz's functions. After uncompressing it, we link the device tree binary to the system's device tree. The kernel can now access the device tree and get the IMC PMUs and their events' information. Not all the IMC PMUs listed in the device tree may be available. This is indicated by imc availability vector (which is a part of the IMC control block structure). We need to check this vector and make sure to remove the IMC device nodes which are unavailable. Signed-off-by: Hemant Kumar <hemant@linux.vnet.ibm.com> Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: use pr_fmt, fix failure path for resource load] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-19capi: Load capp microcodeChristophe Lombard1-1/+1
CAPP microcode flash download and CAPP upload for PHB4. A new file 'capp.c' is created to receive common capp code for PHB3 and PHB4. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-06-08SBE: Add passthrough command supportVasant Hegde1-1/+1
SBE sends passthrough command. We have to capture this interrupt and send event to HBRT via opal-prd (user space daemon). This patch adds minimal SBE code to capture SBE interrupt and send event to opal-prd. Next patch will add opal-prd (user space) support. CC: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-05-10Add global physical memory mapMichael Neuling1-0/+1
This adds a global map for allocating physical memory address. This centralises physical memory space allocations into one location rather than spread through, PHB, XIVE, NX etc. This adds a new call phys_map_get() which takes a chip, type and index and returns a address and size for the region to be used. An error in a call to this function crashes skiboot. This is done since bogus calls here are going to be hit by developers not users and they need to be fixed. Currently only P9 is implemented but other chips should be easy to add. On P9 BARs are generally set by skiboot. On P8 this was done by hostboot so this is not needed there. This just adds the infrastructure. User (PHB4, XIVE etc) will be migrated in subsequent patches. Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-30npu2: Add hardware link training proceduresAlistair Popple1-1/+1
Unlike other system buses the NVLink2 links need to be trained at runtime as training requires interaction from the GPU device drivers. This patch implements the required training procedures for NVLink2, which are different than the NVLink1 equivalents. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-03-30Introduce NPU2 supportAlistair Popple1-1/+1
NVLink2 is a new feature introduced on POWER9 systems. It is an evolution of of the NVLink1 feature included in POWER8+ systems but adds several new features including support for GPU address translation using the Nest MMU and cache coherence. Similar to NVLink1 the functionality is exposed to the OS as a series of virtual PCIe devices. However the actual hardware interfaces are significantly different which limits the amount of common code that can be shared between implementations in the firmware. This patch adds basic hardware initialisation and exposure of the virtual NVLink2 PCIe devices to the running OS. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-02-23hw/lpc-mbox: Add skiboot driver for the AST BMC mbox registersCyril Bur1-1/+1
This adds an internal skiboot API for accessing the AST BMC mbox registers. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-12-13mambo: Add Fake NVRAM driverJack Miller1-0/+1
Implement a fake NVRAM device based on arbitrary memory reserves. This allows NVRAM images to be preloaded without the FSP. Signed-off-by: Jack Miller <jack@codezen.org> Tested-by: Chris Smart <chris@distroguy.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-07-08hw/phb4: Add initial supportBenjamin Herrenschmidt1-2/+4
This adds the base support for the PHB4. It currently only support the M32 window, EEH or in general error recovery aren't supported yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: update (C) year, fix indenting] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2016-07-08XIVE: Base XIVE support for OPAL XICS emulation callsBenjamin Herrenschmidt1-1/+1
This provides basic initialization of the XIVE along with some OPAL calls to emulate an old-style XICS which will initially be used by Linux for backward compatibility. The current implementation is limited to one priority and doesn't expose much to Linux for future exploitation mode yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: add (C) header, fix whitespace, missing breaks] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-11-18Drop support for p5ioc2Daniel Axtens1-1/+1
p5ioc2 is used by approximately 2 machines in the world, and has never ever been a supported configuration. Not only is the code virtually unused and very tricky to test, but keeping it around is making life unnecessarily difficult: - It's more complexity to manage for things such as PCI slot support - It's more code for static analysis to cover, which means more time fixing bugs that affect no-one. - It's bloating every single install of skiboot for no benefit. - It's reducing coverage stats, which is sad. Drop p5ioc2. Signed-off-by: Daniel Axtens <dja@axtens.net> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-10-26Nvlink: Add NPU PHB functionsAlistair Popple1-1/+1
This patch adds support for the NPU Nvlink PHB type. It provides access to each nvlink in the system by exposing them as PCIe devices under a NPU PHB type. Each PCIe device has a configuration space implemented in software which indicates the base address of the DL/TL/PL registers required by the device drivers. It also presents one LSI per device which is used to signal device drivers of changes in device status. The configuration space also adds a vendor specific capability which is used primarily by device drivers to power on an train the IBM PHY. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-07-03plat/qemu: Add LPC based RTC supportBenjamin Herrenschmidt1-1/+1
This adds a driver for standard CMOS RTC chips and use it from the QEMU platform. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-03-24dts: add support to read the core temperaturesCédric Le Goater1-0/+1
This patch adds a new sensor family for Digital Temperature Sensors and a new resource class to capture the core temperatures. Each core has four DTS located in different zones (LSU, ISU, FXU, L3). The max of the four temperatures is computed and returned for the core as well as a global trip point value. This is based on the meltbox tool. Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-03-04hw/prd: Add firmware PRD handling subsystemJeremy Kerr1-1/+1
This change adds Processor Recovery Diagnostics (PRD) code to skiboot firmware. This allows certain hardware RAS events to be handled by a userspace application. The core of the PRD code is a messaging interface to the kernel (and onwards to userspace). PRD events are logged with the prd.c code, and sent to the kernel as opal_msg messages. For responses to these messages, the kernel will reply using a new OPAL call, opal_prd_msg. Only one message is outstanding at a time; we collect events from hardware interrupts (hooked up by subsequent patches), and set per-processor event bits. Once an event has been consumed by the kernel, we clear that event from out pending set, and send any further pending events. Certain events (hardware attentions from the psi layer) need to be masked at interrupt time. For these, we have an acknowledgement facility to clear the mask once the userspace PRD application has cleared the source of the error. Includes multiple contributions from: Neelesh Gupta <neelegup@linux.vnet.ibm.com> Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Neelesh Gupta <neelegup@linux.vnet.ibm.com> Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2015-02-19add nx-842 coproc supportDan Streetman1-1/+2
Add support for the 842 hw memory compression engine in the NX Coprocessor. This moves the existing RNG support into its own nx-rng.c file, adds 842 support in a nx-842.c file, and creates a nx-crypto.c file to configure and disable the crypto engines (which are not supported yet). New nodes are created for each 842 engine found. This does not actually process any of the data or drive the 842 engines, it only configures registers to set up and enable/disable the engines appropriately, and creates new nodes so the OS can drive the 842 engines. Signed-off-by: Dan Streetman <ddstreet@ieee.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2014-10-27hw/i2c: i2c driver infrastructure providing device I/ONeelesh Gupta1-1/+1
This patch adds the generic i2c driver infrastructure to handle multiple i2c master cores present in the system and exposes structures and interfaces for the client to perform I/O on the i2c slave devices. The driver adds the capability to queue multiple requests from client and let clients notified asynchronously after completion. It does that by handling the i2c interrupt or through OPAL poller in the absence of interrupt. Signed-off-by: Neelesh Gupta <neelegup@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2014-10-01ipmi: Refactored ipmi layer to use generic backendAlistair Popple1-2/+2
The initial implementation of the ipmi stack was still tightly coupled with the backend (in this case bt). This patch refactors the ipmi code to use a generic backend device. The core ipmi messaging functionality and the implementation of specific commands has also been split into different files. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-08-13ipmi: Add a base IPMI stack with a BT driverAlistair Popple1-1/+1
This patch adds a basic IPMI layer to the sapphire core and support for a BT IPMI interface as found on the Aspeed BMC of the Palmetto platform [ Changed the compatible property -- BenH ] Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-08-08Add fake RTC to generic platformmillerjo@us.ibm.com1-1/+1
Adds a fake RTC that can be initialized via a named reserve in the device tree that may, at some point, be on NVRAM. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2014-07-02Initial commit of Open Source releaseBenjamin Herrenschmidt1-0/+15
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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