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2021-10-19pau: introduce supportChristophe Lombard1-7/+24
OpenCapi for P10 is included in the P10 chip. This requires OCAPI capable PHYs, Datalink Layer Logic and Transaction Layer Logic to be included. The PHYs are the physical connection to the OCAPI interconnect. The Datalink Layer provides link training. The Transaction Layer executes the cache coherent and data movement commands on the P10 chip. The PAU provides the Transaction Layer functionality for the OCAPI link(s) on the P10 chip. The P10 PAU supports two OCAPI links. Six accelerator units PAUs are instantiated on the P10 chip for a total of twelve OCAPI links. This patch adds PAU opencapi structure for supporting OpenCapi5. hw/pau.c file contains main of PAU management functions. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06phys/P10: Use topology index to get phys mappingVasant Hegde1-0/+28
This fixes multipchip rainier boot issue. for Rainer: chip0: ibm,primary-topology-index = < 0x0>; chip1: ibm,primary-topology-index = < 0x4>; chip2: ibm,primary-topology-index = < 0x8>; chip3: ibm,primary-topology-index = < 0xc>; for Denali: node0: chip0: ibm,primary-topology-index = < 0x0>; chip1: ibm,primary-topology-index = < 0x1>; chip2: ibm,primary-topology-index = < 0x2>; chip3: ibm,primary-topology-index = < 0x3>; node1: chip0: ibm,primary-topology-index = < 0x4>; chip1: ibm,primary-topology-index = < 0x5>; chip2: ibm,primary-topology-index = < 0x6>; chip3: ibm,primary-topology-index = < 0x7>; Note that bmc_create_node() gets called very early in the boot process. Hence we have to traverse through HDAT ntuple to get right topology index. May be we can optimize pcid_to_topology_idx() function as its pretty much duplicate of pcid_to_chip_id(). But for now lets keep it as separate function. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Ryan Grimm <grimm@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hdata/P10: Fix xscom address and ibm, chip-id propertyVasant Hegde1-11/+23
`xscom_id` is deprecated in P10. Instead we should use topology ID's ("Primary topology table index") to calculate xscom address. Also use ("Processor fabric topology id") for "ibm,chip-id" property. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hdat/spira: Add ibm, power10-vas-x string to VAS compatible propertyHaren Myneni1-9/+16
VAS SCOM base address and paste address format are changed on P10. This patch adds ibm,power10-vas-x string to compatible property per each VAS node. This compatible string is used to define the paste base address later during VAS initialization. Also enables NX on P10 without adding any compatible string since the NX SCOM base address is not changed. Signed-off-by: Haren Myneni <haren@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hdat/spira: Define ibm, primary-topology-index property per chipHaren Myneni1-0/+12
HDAT provides Topology ID table and the primary topology location on P10. This primary location points to primary topology entry in ID table which contains the primary topology index and this index is used to define the paste base address per chip. This patch reads Topology ID table and the primary topology location from hdata and retrieves the primary topology index in the ID table. Make this primaty topology index value available with ibm,primary-topology-index property per chip. VAS reads this property to setup paste base address for each chip. Signed-off-by: Haren Myneni <haren@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-08-06hdata: Add POWER10 supportVasant Hegde1-7/+45
Initial P10 support - LPC : This contains two useful information: LPC MCTP Memory Window Base Address Second vUART console details - Enable memory-buffer mmio - Fix ipmi sensors IPMI sensors are deprecated in P10. Hence do not parse ipmi sensors. - I2C support - Detect PHB5 - Create p10 xscom, xive, chiptod nodes - Set pa-features bit for 2nd DAWR Availability of 2nd DAWR depends on 0th bit of 64th byte of ibm,pa-features property. Set it for p10. Co-authored-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Co-authored-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Co-authored-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Co-authored-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com> Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2020-12-15hdata: assert if we fail to add xscom nodesVasant Hegde1-2/+1
If we have duplicate xscom nodes then it will fail to attach xscom node to device tree and we will fail eventully. Better to call assert() and fail here. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2020-10-01hdata/spira: add physical presence flagsNayna Jain1-0/+11
This patch reads the hdata bits to check for physical presence assertion, and creates device tree entries to be consumed later in the boot. Signed-off-by: Nayna Jain <nayna@linux.ibm.com> Signed-off-by: Eric Richter <erichte@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-03-12Re-license IBM written files as Apache 2.0 OR GPLv2+Stewart Smith1-1/+1
SPDX makes it a simpler diff. I have audited the commit history of each file to ensure that they are exclusively authored by IBM and thus we have the right to relicense. The motivation behind this is twofold: 1) We want to enable experiments with coreboot, which is GPLv2 licensed 2) An upcoming firmware component wants to incorporate code from skiboot and code from the Linux kernel, which is GPLv2 licensed. I have gone through the IBM internal way of gaining approval for this. The following files are not exclusively authored by IBM, so are *not* included in this update (I will be seeking approval from contributors): core/direct-controls.c core/flash.c core/pcie-slot.c external/common/arch_flash_unknown.c external/common/rules.mk external/gard/Makefile external/gard/rules.mk external/opal-prd/Makefile external/pflash/Makefile external/xscom-utils/Makefile hdata/vpd.c hw/dts.c hw/ipmi/ipmi-watchdog.c hw/phb4.c include/cpu.h include/phb4.h include/platform.h libflash/libffs.c libstb/mbedtls/sha512.c libstb/mbedtls/sha512.h platforms/astbmc/barreleye.c platforms/astbmc/garrison.c platforms/astbmc/mihawk.c platforms/astbmc/nicole.c platforms/astbmc/p8dnu.c platforms/astbmc/p8dtu.c platforms/astbmc/p9dsu.c platforms/astbmc/vesnin.c platforms/rhesus/ec/config.h platforms/rhesus/ec/gpio.h platforms/rhesus/gpio.c platforms/rhesus/rhesus.c platforms/astbmc/talos.c platforms/astbmc/romulus.c Signed-off-by: Stewart Smith <stewart@linux.ibm.com> [oliver: fixed up the drift] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-02-12hdata: Fix SP attention area addressVasant Hegde1-1/+2
SP attention area is aligned. We were sending wrong address. Hence `attn` on FSP based system is failing. Align SP attention area so that FSP can locate attention data. Fixes: 518e554 (spira: fix endian conversions in spira data structures) CC: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2020-01-29npu2, npu3: Remove ibm, phb-index property from the NPU dt nodeFrederic Barrat1-4/+2
The 'ibm,phb-index' property of the NPU node is now useless, as we can have multiple PHBs associated to the same NPU on P9. Let's remove it to avoid confusion. Reviewed-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-16add more sparse endian annotationsNicholas Piggin1-1/+1
This fixes quite a few sparse endian annotations across the tree. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-16naca: move naca definition from asm to CNicholas Piggin1-7/+4
This results in the same layout and location of the naca and hv data structures. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-16hdata: endian conversionsNicholas Piggin1-3/+3
Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-12-16spira: fix endian conversions in spira data structuresNicholas Piggin1-22/+37
Labels can't be used for static initialisers that require endian conversion. Use constants for these. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-11Remove dead POWER7 codeNicholas Piggin1-8/+3
There are a number of proc_gen branches removed that are trivially dead code and comments that refer to P7. As well as those: - Oliver points out that add_xics_icps() must be unused on POWER8 because it asserts if number of threads > 4, so remove it. - Change 16b7ae641 ("Remove POWER7 and POWER7+ support") removed all references to opal_boot_trampoline, so remove that. - It also removed the only non-trival choose_bus implementation, so that is removed and its caller simplified. - Remove the paca code, later CPUs use pcia. Cc: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-11-07hdata: Add a generic compatible to ibm,securebootOliver O'Halloran1-1/+2
Add a way to locate the secureboot node without needing to hardcode a specific version string. The ibm,secureboot node has historically only been used by firmware. Signed-off-by: Eric Richter <erichte@linux.ibm.com> [oliver: removed extra whitespace] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-10-03hdat/spira: export abc and wxyz bus speedsMadhavan Srinivasan1-0/+11
One of the spira structs (iplparams_sysparams) captures different system bus speeds/frequency. Patch exports the same in "sys-params" dt node. These values will help in nest pmu metric calculations. ABC bus speed values are exported in "abc-bus-freq-mhz" property. As name suggest, values are in MHz. WXYZ bus speed values are exported in "wxyz-bus-freq-mhz" property. As name suggest, values are in MHz. Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> [oliver: added missing s-o-b, fixed hdat tests] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15MPIPL: Reserve memory to capture architected registers dataVasant Hegde1-0/+7
- Split SPIRAH memory to accommodate architected register ntuple. Today we have 1K memory for SPIRAH and it uses 288 bytes. Lets split this into two parts : SPIRAH (756 bytes) architected register memory (256 bytes) - Update SPIRAH architected register ntuple - Calculate memory required to capture architected registers data Ideally we should use HDAT provided data (proc_dump_area->thread_size). But we are not getting this data during boot. Hence lets reserve fixed memory for architected registers data collection. - Add architected registers destination memory to reserve-memory DT node. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15hdata: Add "mpipl-boot" property to "dump" nodeVasant Hegde1-0/+43
During MPIPL boot, hostboot updates HDAT to indicate its MPIPL boot. Lets add "mpipl-boot" property to device tree. So that kernel can detect its MPIPL boot and create dump. Device tree property: /ibm,opal/dump/mpipl-boot - Indicate kernel that its MPIPL boot Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15hdata: Create /ibm, opal/dump device tree nodeVasant Hegde1-0/+21
We use MPIPL system parameter to detect whether MPIPL is supported or not. If its supported create new device tree node (/ibm,opal/dump) to pass all dump related information to kernel. This patch creates new node and populates below properties: - compatible - dump version (ibm,opal-dump) - fw-load-area - Memory used by OPAL to load kernel/initrd from PNOR (KERNEL_LOAD_BASE & INITRAMFS_LOAD_BASE). This is the temporary memory used by OPAL during boot. Later Linux kernel is free to use this memory. During MPIPL boot also OPAL will overwrite this memory. OPAL will advertise these memory details to kernel. If kernel is using these memory and needs these memory content for proper dump creation, then it has to reserve destination memory to preserve these memory ranges. Also kernel should pass this detail during registration. During MPIPL firmware will take care of preserving memory and post MPIPL kernel can create proper dump. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15hdata: Adjust various structure offset after relocationVasant Hegde1-0/+23
ntuple addresses in SPIRAH are relative to payload base. Update various addresses after relocation so that hostboot can access new address to capture dump. Note that we update relocated SPIRAH. So future if we add early OPAL crash support, hostboot can still collect dump using origianl skiboot base. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15hdata: Update spirah structureVasant Hegde1-3/+24
Update MDST, MDDT and MDRT ntuple inside SPIRAH. During MPIPL hostboot will use these details to preserve memory. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15hdata: Define various DUMP related structuresVasant Hegde1-0/+1
- MDDT is used by OPAL to pass destination memory details to hostboot. - MDRT is used by hostboot to pass post dump result table to OPAL. - Processor dump area is used to capture architected register data. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15hdata: Split MDST 'type' field to accommodate MPIPLVasant Hegde1-2/+4
The MPIPL facility needs to store region and type information corresponding with each MDST entry. - data region : dump data regions (like DUMP_REGION_* ) - dump type : Reflects MDST entry usage (used by SYSDUMP -OR- FADUMP) The existing type field is currently not used by FSP and/or firmware, so it is safe to re-purpose it. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-08-15FSP/MDST: Rename fsp-mdst-table.c -> fsp-sysdump.cVasant Hegde1-3/+3
MDST is a ntuple inside SPIRAH. Its just a interface to pass memory ranges to be captured as part of dump to FSP/Hostboot. Today OPAL is using MDST ntuple to pass list of memory region (mostly OPAL console and host dmesg) to be collected as part of SYSDUMP. Soon we are going to support OPAL MPIPL feature (aka Memory Preserving IPL). Even MPIPL uses MDST/MDDT table. Hence rename files based on feature instead of some table name: - fsp-mdst-table.c -> fsp-sysdump.c - fsp-mdst-table.h -> opal-dump.h (This will cater both SYSDUMP and MPIPL) - Rename structure -> dump_mdst_table -> mdst_table This patch does renaming and header file adjustment. No functionality changes. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [oliver: rebased] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26npu2: Add checks to npu2-only codepathsReza Arbab1-3/+3
To prepare for npu3, add a few checks in codepaths that are only for npu2. Compare against PVR_TYPE_P9, as npu3 will be in systems of PVR_TYPE_P9P (or greater). Alternatively, check for dt compatibility with "ibm,power9-npu" because npu3 will use "ibm,power9-npu3". Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-26SPDX-ify all skiboot codeStewart Smith1-15/+2
Use Software Package Data Exchange (SPDX) to indicate license for each file that is unique to skiboot. At the same time, ensure the (C) who and years are correct. See https://spdx.org/ Signed-off-by: Stewart Smith <stewart@linux.ibm.com> [oliver: Added a few missing files] Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-19sparse: hdata/spira sw_xstop_fir_bitpos is uint8_t, has no endianStewart Smith1-2/+2
hdata/spira.c:625:33: warning: incorrect type in argument 1 (different base types) hdata/spira.c:625:33: expected restricted beint32_t [usertype] be_val hdata/spira.c:625:33: got unsigned char [usertype] fir_bit hdata/spira.c:625:33: warning: incorrect type in argument 1 (different base types) hdata/spira.c:625:33: expected restricted beint32_t [usertype] be_val hdata/spira.c:625:33: got unsigned char [usertype] fir_bit Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-19sparse: various SPIRA structures, declare them.Stewart Smith1-0/+7
hdata/spira.c:42:49: warning: symbol 'proc_init_data' was not declared. Should it be static? hdata/spira.c:51:49: warning: symbol 'cpu_ctl_spat_area' was not declared. Should it be static? hdata/spira.c:54:49: warning: symbol 'cpu_ctl_hsr_area' was not declared. Should it be static? hdata/spira.c:56:53: warning: symbol 'cpu_ctl_init_data' was not declared. Should it be static? hdata/spira.c:92:48: warning: symbol 'init_mdst_table' was not declared. Should it be static? Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
2019-07-15npu2-opencapi: Add opencapi support on ZZFrederic Barrat1-1/+8
This patch adds opencapi support on ZZ. It hard-codes the required device tree entries for the NPU and links. The alternative was to use HDAT, but it somehow proved too painful to do. The new device tree entries activate the npu2 init code on ZZ. On systems with no opencapi adapters, it should go unnoticed, as presence detection will skip link training. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-07-15hdata: Align SMP link definitions with current HDAT specFrederic Barrat1-1/+1
All link usage values other than GPU were unused, so there's no functional change or backward compatibility issue. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-06-04Remove POWER7 and POWER7+ supportStewart Smith1-113/+1
It's been a good long while since either OPAL POWER7 user touched a machine, and even longer since they'd have been okay using an old version rather than tracking master. There's also been no testing of OPAL on POWER7 systems for an awfully long time, so it's pretty safe to assume that it's very much bitrotted. It also saves a whole 14kb of xz compressed payload space. Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Enthusiasticly-Acked-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2019-03-20hdata: Add protection against corrupt ntuples structureStewart Smith1-0/+21
Found using afl-lop on P9 HDAT. Pretty obvious what the problem is once you look at it, and it's much better having a controlled failure mode than just going off randomly into memory and segfaulting. Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-09-27hdata: Explain what the xscom node bus-frequency isOliver O'Halloran1-1/+4
Vague documentation is about as annoying as no documentation. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-09-17hw/npu2, platform: Add NPU2 platform device detection callbackAndrew Donnellan1-1/+0
There is no standardised way to determine the presence and type of devices connected to an NPU on POWER9. Currently, we hardcode device types based on platform type (as no platform currently supports both OpenCAPI and NVLink), and for OpenCAPI platforms we use I2C to detect presence. Witherspoon (and potentially other platforms later on) supports both NVLink and OpenCAPI, and additionally uses SXM2 connectors which can carry more than one link, rather than the SlimSAS connectors used for OpenCAPI on Zaius and ZZ. This necessitates some special handling. Add a platform callback for NPU device detection. In a later patch, we will use this to implement Witherspoon-specific device detection. For now, add a Witherspoon stub that sets all links to NVLink (i.e. current behaviour). Move the existing I2C-based presence detection for OpenCAPI devices on Zaius/ZZ into common code, which we use by default for platforms which do not define a callback. Clean up the use of the ibm,npu-link-type property, which will now be exposed solely for debugging and not consumed internally. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-09-13hdata: Make sure FW feature name is not emptyVasant Hegde1-0/+5
CC: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2018-07-03npu2: Use same compatible string for NVLink and OpenCAPI link nodes in ↵Andrew Donnellan1-0/+1
device tree Currently, we distinguish between NPU links for NVLink devices and OpenCAPI devices through the use of two different compatible strings - ibm,npu-link and ibm,npu-link-opencapi. As we move towards supporting configurations with both NVLink and OpenCAPI devices behind a single NPU, we need to detect the device type as part of presence detection, which can't happen until well after the point where the HDAT or platform code has created the NPU device tree nodes. Changing a node's compatible string after it's been created is a bit ugly, so instead we should move the device type to a new property which we can add to the node later on. Get rid of the ibm,npu-link-opencapi compatible string, add a new ibm,npu-link-type property, and a helper function to check the link type. Add an "unknown" device type in preparation for later patches to detect device type dynamically. These device tree bindings are entirely internal to skiboot and are not consumed directly by Linux, so this shouldn't break anything (other than internal BML lab environments). Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-06-27vpd: Add vendor property to processor nodeVasant Hegde1-0/+2
Processor FRU vpd doesn't contain vendor detail. We have to parse module VPD to get vendor detail. Reported-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-06-05Quieten console output on bootStewart Smith1-1/+1
We print out a whole bunch of things on boot, most of which aren't interesting, so we should *not* print them instead. Printing things like what CPUs we found and what PCI devices we found *are* useful, so continue to do that. But we don't need to splat out a bunch of things that are always going to be true. Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-05-29hdata/spira.c: fix iplparams feature name string handlingStewart Smith1-1/+3
Fixes this gcc8 warning: hdata/test/../spira.c: In function ‘add_iplparams_features’: hdata/test/../spira.c:1209:38: error: argument to ‘sizeof’ in ‘strncpy’ call is the same expression as the source; did you mean to use the size of the destination? [-Werror=sizeof-pointer-memaccess] strncpy(name, feature->name, sizeof(feature->name)); ^ Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-04-30hdata: Add 'primary' property to master chip xscom nodeVasant Hegde1-1/+4
Needed for SBE communication as some of the SBE MBOX commands has to be sent to SBE on master chip only. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-04-23hdata/slots: Apply slot label to the parent slotOliver O'Halloran1-1/+7
Slot names only really make sense when applied to an actual slot rather than a device. On witherspoon the GPU devices have a name associated with the device rather than the slot for the GPUs. Add a hack that moves the slot label to the parent slot rather than on the device itself. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-04-11hdata/spira: parse vpd to add part-number and serial-number to xscom@ nodeStewart Smith1-1/+3
Expected by FWTS and associates our processor with the part/serial number, which is obviously a good thing for one's own sanity. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-04-11hdata: Move 'HRMOR_BIT' macro to header fileVasant Hegde1-3/+2
Its already defined twice. And soon I want to use in few other place. Lets move it to header file. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
2018-01-05hdata: Parse IPL FW feature settingsOliver O'Halloran1-0/+47
Add parsing for the firmware feature flags in the HDAT. This indicates the settings of various parameters which are set at IPL time by firmware. Cc: stable # 5.4.x 371e88e23662 eeba2d64fb7a 0abc3af7e8f6 Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-18hdata/tpmrel.c: add firmware event log info to the tpm nodeClaudio Carvalho1-0/+4
This parses the firmware event log information from the secureboot_tpm_info HDAT structure and add it to the tpm device tree node. There can be multiple secureboot_tpm_info entries with each entry corresponding to a master processor that has a tpm device, however, multiple tpm is not supported. Signed-off-by: Claudio Carvalho <cclaudio@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-18hdata/spira: add ibm, secureboot node in P9Claudio Carvalho1-0/+39
In P9, skiboot builds the device tree from the HDAT. These are the "ibm,secureboot" node changes compared to P8: - The Container-Verification-Code (CVC), a.k.a. ROM code, is no longer stored in a secure ROM with static address. In P9, it is stored in a hostboot reserved memory and each service provided also has a version, not only an offset. - The hash-algo property is not provided via HDAT, instead it provides the hw-key-hash-size, which is indeed the information required by the CVC to verify containers. This parses the iplparams_sysparams HDAT structure and creates the "ibm,secureboot", which is bumped to "ibm,secureboot-v2". In "ibm,secureboot-v2": - hash-algo property is superseded by hw-key-hash-size. - container verification code is explicitly described by a child node. Added in a subsequent patch. Signed-off-by: Claudio Carvalho <cclaudio@linux.vnet.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Reviewed-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-18hdata: add secure and trusted boot ntuple to SPIRA-H/SClaudio Carvalho1-0/+1
This adds to spira-h/s the overall tpmrel structure, which defines secure and trusted boot related data. The internal data structures are added in subsequent patches. Signed-off-by: Claudio Carvalho <cclaudio@linux.vnet.ibm.com> Reviewed-by: Oliver O'Halloran <oohall@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-12-18hdata: Add memory hierarchy under xscom nodeVasant Hegde1-3/+3
We have memory to chip mapping but doesn't have complete memory hierarchy. This patch adds memory hierarchy under xscom node. This is specific to P9 system as these hierarchy may change between processor generation. It uses memory controller ID details and populates nodes like: xscom@<addr>/mcbist@<mcbist_id>/mcs@<mcs_id>/mca@<mca_id>/dimm@<resource_id> Also this patch adds few properties under dimm node. Finally make sure xscom nodes created before calling memory_parse(). Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
generated by cgit v1.1 at 2024-09-09 11:35:02 +0000