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The XIVE2 interrupt controller of the POWER10 processor follows the
same logic than on POWER9 but the HW interface has been largely
reviewed. It has a new register interface, different BARs, extra
VSDs, new layout for the XIVE structures, and a set of new features
which are described below.
The OPAL XIVE2 driver code activating this controller was duplicated
from P9 for clarity as the registers and structures have changed
considerably. The same OPAL interface is implemented for OS
compatibility and it should not impact existing Linux kernels, KVM
included. Guest OS is not impacted either.
Support for new features will be implemented in time and will require
new support from the OS.
* XIVE2 BARS
The interrupt controller BARs have a different layout outlined below.
Each sub-engine has now own its range and the indirect TIMA access was
replaced with a set of pages, one per CPU, under the IC BAR:
- IC BAR (Interrupt Controller)
. 4 pages, one per sub-engine
. 128 indirect TIMA pages
- TM BAR (Thread Interrupt Management Area)
. 4 pages
- ESB BAR (ESB pages for IPIs)
. up to 1TB
- END BAR (ESB pages for ENDs)
. up to 2TB
- NVC BAR (Notification Virtual Crowd)
. up to 128
- NVPG BAR (Notification Virtual Process and Group)
. up to 1TB
- Direct mapped Thread Context Area (reads & writes)
OPAL does not use the grouping and crowd capability.
* Virtual Structure Tables
XIVE2 adds new tables types and also changes the field layout of the END
and NVP Virtualization Structure Descriptors.
- EAS
- END new layout
- NVT was splitted in :
. NVP (Processor), 32B
. NVG (Group), 32B
. NVC (Crowd == P9 block group) 32B
- IC for remote configuration
- SYNC for cache injection
- ERQ for event input queue
The setup is slighly different on XIVE2 because the indexing has changed
for some of the tables, block ID or the chip topology ID can be used.
* XIVE2 features
SCOM and MMIO registers have a new layout and XIVE2 adds a new global
capability and configuration registers.
The lowlevel hardware offers a set of new features among which :
- cache injection mechanism
- 4 cache watch engines
- a configurable number of priorities : 1 -8
- StoreEOI with load-after-store ordering is activated by default
- new sync/kill operations for cache operations
Other features will have some impact on the Hypervisor and guest OS
when activated, but this is not required for initial support of the
controller.
- Gen2 TIMA layout
- A P9-compat mode, or Gen1, TIMA toggle bit for SW compatibility
- Automatic Context save & restore
- increase to 24bit for VP number
- New escalations schems : ESB, Adaptive, CPPR
POWER10 adds support for User interrupts. When configured, the XIVE2
controller can notify directly user processes using the Event Based
Branch exception line of the thread. If not running, the OS is
notified through an escalation event. New OPAL and PAPR interfaces
will be required and OS support needs to be studied.
* XIVE2 P9-compat mode, or Gen1
The thread interrupt management area (TIMA) is a set of pages mapped
in the Hypervisor and in the guest OS address space giving access to
the interrupt thread context registers for interrupt management, ACK,
EOI, CPPR, etc.
XIVE2 changes slightly the TIMA layout with extra bits for the new
features, larger CAM lines and the controller provides configuration
switches for backward compatibility. This is called the XIVE2
P9-compat mode, of Gen1 TIMA. It impacts the layout of the TIMA and
the availability of the internal features associated with it,
Automatic Save & Restore for instance. Using a P9 layout also means
setting the controller in such a mode at init time.
The XIVE2 driver in OPAL chooses to initialize the XIVE2 controller
with a XIVE2/P10 TIMA directly because the layouts are compatible with
the Linux PowerNV and the guest OSes expectations.
For KVM support, the OPAL calls abstract the HW interface and no
assumption is made on the OS CAM line width.
* Activating new XIVE2 features
Everything related to OPAL internals such as the use of the new cache
sync mechanism can be implemented in time without impact on the OS.
Other features will require new device tree properties exposed to the
OS and extra support for the OS. Automatic Context save & restore is
one of the first feature which should be looked at.
* XICS-over-XICS driver (P8 compatibility)
The P8 emulation mode is an OPAL compat interface used for Linux
kernels which did not have XIVE native support. This was useful for
POWER9 bringup but it is much less now. As it was adding a lot of
complexity and reducing the interrupt controller resources, this mode
is not available in the XIVE2 driver for POWER10.
It will still be possible to add this compat mode in the future if
required. The OS will have to reset the driver at boot time, like on
POWER9.
* Impact on other drivers (PSI, PHB, NPU)
Interrupts are allocated in a very similar way. Each controller might
have different ESB characteristics, StoreEOI support, 64K pages for
PSI. All is in place to support these changes already.
PHB5 will have support for "address-based trigger mode", probably in
the DD2.0 time frame when verification is completed. When activated,
the XIVE IC ESB pages will be used instead of the PHB ESB pages for a
lower interrupt latency.
LSI will still use old fashion triggers without StoreEOI.
* Yet to be addressed :
- OPAL P10 interface incomplete (stop states)
- Clarify the PHB5 strategy regarding the use of the XIVE IC ESB
pages instead of the PHB ones when address-based trigger mode is
supported.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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This works around a core recovery issue in P10. The workaround involves
the CME polling for a core recovery and performing the recovery
procedure itself.
For this to happen, the host leaves core recovery off (HID[5]) and
then masks the PC system checkstop. This patch does this.
Firmware starts skiboot with recovery already off, so we just leave it
off for longer and then mask the PC system checkstop. This makes the
window longer where a core recovery can cause an xstop but this
window is still small and can still only happens on boot.
Signed-off-by: Michael Neuling <mikey@neuling.org>
[Added mambo check - Vasant]
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Co-authored-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Co-authored-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com>
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com>
Co-authored-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Co-authored-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Co-authored-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Co-authored-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Previously we put all the trace buffer exports in the exports/ node.
However, there's one trace buffer for each core so I moved them into a
subdirectory since they were crowding up the place. Most kernels don't
support recursively exporting subnodes though so kernel's don't have
support for recursively exporting subnodes, so add a hack to restore the
old behaviour for now.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
[Fixed run-trace test case - Vasant]
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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imc_init() checks for the 24x7 microcode state at boot to
check whether the microcode is in proper state (running or paused).
But in a larger system, loading of 24x7 microcode by OCC gets delayed.
Because of this, imc_init() removes imc devices from the device tree.
Moving imc_init() function towards end of the main_cpu_entry()
works around this.
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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OS Secure Boot establishes a chain of trust from firmware to the OS.
However, OS Secure Boot can only be secure if the chain of trust
beneath it - from hardware to firmware - has been established by
Firmware Secure Boot. This patch ensures that OS Secure Boot is enabled
only if Firmware Secure Boot is enabled.
Signed-off-by: Nayna Jain <nayna@linux.ibm.com>
Signed-off-by: Eric Richter <erichte@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Previous commit 482f18adf21eeb5f6ce2a93334725509a8f6f0cd
added check for fused core mode and bailed out.
The check can be removed since fused core mode
is now supported in OPAL.
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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If OPAL boot fails after MPIPL init (opal_mpipl_init()) then we call MPIPL
boot instead of reboot. BMC is not aware of MPIPL. Hence it may result in
continuous MPIPL loop (boot -> crash -> MPIPL -> boot).
If OPAL boot fails (before loading kernel) then its better to call reboot.
So that BMC can detect `n` number of boot failures (generally n = 3) and
stop booting. That way we can avoid continuous loop.
This patch moves MPIPL init to the end of init process (just before starting
kernel). So that if we fail to boot OPAL we call normal reboot.
Also this patch introduces new function to detect MPIPL is enabled or not
(is_mpipl_enabled()). And in assert() path we check for this function
instead of `dump` DT node. So that it will make sure we will not call
MPIPL until opal_mpipl_init is complete.
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Initial boot already saved original exception vectors to old_vectors,
copying again upon fast reboot will overwrite old_vectors with some
arbitrary vectors set up by the current OS.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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This patch disables Protected Execution Faciltiy (PEF).
This software procedure is needed for the lab because Cronus will be
configured to bring the machine up with PEF on. Hostboot has a similar
procedure for running with PEF off.
Skiboot can run with PEF on but the kernel cannot; the kernel will take
a machine check when trying to write a protected resource, such as the
PTCR.
So, use this until we have an ultravisor, or if we want to use BML with
Cronus without UV = 1.
Signed-off-by: Ryan Grimm <grimm@linux.ibm.com>
Tested-by: Alistair Popple <alistair@popple.id.au>
[oliver: replaced bare urfid with a macro for toolchain compatibility]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Fused code mode is currently not supported in OPAL. Continuing to
boot the system would result in errors at later stages of boot.
Wait for console to be up and print message for developers to check
and fix the system modes.
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Tested-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Add a driver for the SCOM ranges of the OCMB. Unlike most chips the OCMB
has two different (three if you count OpenCAPI config space) register
spaces and we need to ensure that the right access size is used on each.
Additionally the SCOM interface is a bit non-standard in that a full
physical address is passed as the SCOM address rather than a register
number so we don't need to perform any address transformations, we just
need to verify that the address falls into one of the nominated address
ranges.
Cc: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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SPDX makes it a simpler diff.
I have audited the commit history of each file to ensure that they are
exclusively authored by IBM and thus we have the right to relicense.
The motivation behind this is twofold:
1) We want to enable experiments with coreboot, which is GPLv2 licensed
2) An upcoming firmware component wants to incorporate code from skiboot
and code from the Linux kernel, which is GPLv2 licensed.
I have gone through the IBM internal way of gaining approval for this.
The following files are not exclusively authored by IBM, so are *not*
included in this update (I will be seeking approval from contributors):
core/direct-controls.c
core/flash.c
core/pcie-slot.c
external/common/arch_flash_unknown.c
external/common/rules.mk
external/gard/Makefile
external/gard/rules.mk
external/opal-prd/Makefile
external/pflash/Makefile
external/xscom-utils/Makefile
hdata/vpd.c
hw/dts.c
hw/ipmi/ipmi-watchdog.c
hw/phb4.c
include/cpu.h
include/phb4.h
include/platform.h
libflash/libffs.c
libstb/mbedtls/sha512.c
libstb/mbedtls/sha512.h
platforms/astbmc/barreleye.c
platforms/astbmc/garrison.c
platforms/astbmc/mihawk.c
platforms/astbmc/nicole.c
platforms/astbmc/p8dnu.c
platforms/astbmc/p8dtu.c
platforms/astbmc/p9dsu.c
platforms/astbmc/vesnin.c
platforms/rhesus/ec/config.h
platforms/rhesus/ec/gpio.h
platforms/rhesus/gpio.c
platforms/rhesus/rhesus.c
platforms/astbmc/talos.c
platforms/astbmc/romulus.c
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
[oliver: fixed up the drift]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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During boot, OPAL reserves memory required to capture OPAL dump and
architected register data. During MPIPL, hostboot will copy OPAL dump
to this memory. Post MPIPL kernel will use this memory to create opalcore.
We use mem_reserve_fw() for this reservation. At present this reservation
happens late in the init path. It may clash with memory allocated by
local_alloc().
We have two option to fix above issue:
- Use local_alloc() for allocating memory for OPAL dump
This works fine on first boot. We can use this method to reserve
memory. But Post MPIPL we still want to reserve destination
memory to make sure no one is stomping this area. Also this reservation
might have happened in between other local_allocations. So in Post MPIPL
boot allocator may not find enough memory in first region for other
local_alloc() requests and may throw mem_alloc() error before trying to
allocate from other regions.
- Early memory reservation for OPAL dump
Allocate and reserve memory just after memory region init.
This patch uses second approach to fix reservation issue.
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Should be no real code change, these mostly update type declarations
that sparse complains about.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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This adds support for building LE skiboot with LITTLE_ENDIAN=1.
This is not complete, notably PHB3, NPU* and *CAPI*, but it is
sufficient to build and boot on mambo and OpenPOWER POWER9 systems.
LE/ELFv2 is a nicer calling convention, and results in smaller image and
less stack usage. It also follows the rest of the Linux/OpenPOWER stack
moving to LE.
The OPALv3 call interface still requires an ugly transition through BE
for compatibility, but that is all handled on the OPAL side.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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LoPAPR says:
“ibm,processor-storage-keys”
property name indicating the number of virtual storage keys supported
by the processor described by this node.
prop-encoded-array: Consists of two cells encoded as with encode-int.
The first cell represents the number of virtual storage keys supported
for data accesses while the second cell represents the number of
virtual storage keys supported for instruction accesses. The cell value
of zero indicates that no storage keys are supported for the access
type.
pHyp provides the property above but there's a bug in P8 firmware
where the second cell is zero even though POWER8 supports instruction
access keys. This bug will be fixed for P9.
While this is a PAPR property, it's useful to have it in powernv as
well so that Linux has a uniform way of checking for the feature
regardless of the platform it's running on.
Tested on QEMU POWER8 powernv model, Mambo P9 and POWER8 Firenze
machine.
Signed-off-by: Thiago Jung Bauermann <bauerman@linux.vnet.ibm.com>
[mpe: Rebase, add comment explaining why we hard code 32]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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BUILD_ASSERT can not be used for constants generated by the assembler
or linker. This results in variable length arrays that do not catch
the failure condition. This was caught by sparse.
Remove these and add some equivalent as/ld checks which actually do
the right thing.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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This patch implements a platform-independent abstraction for storing and
retrieving secure variables, as required for host OS secure boot. This
serves as the main entry point for initializing the in-memory cache of the
secure variables, which also kicks off any platform-specific logic that may
be needed. This patch also provides core functions for the subsequent
patches in this series to utilize.
The base secure variable implementation makes use of two types of
drivers, to be selected by the platform: "storage" drivers, and
"backend" drivers. The storage driver implements the hooks required to
write the secure variables to some form of non-volatile memory, and load
the variables on boot. The backend driver defines how the variables
should be interpreted, and processed.
Secure variables are stored in two types of banks, the "variable" bank
and the "update" bank. Variables that have been validated and processed
are stored in the variable bank. This bank is effectively read-only
after the base secvar initialization. Any proposed variable updates are
instead stored in the update bank. During secvar initialization, the
backend driver processes variables from the update bank, and if valid,
adds the new variable to the variable bank.
NOTE: The name "backend" is subject to change. It operates more like a
scheme, so unless a better name comes along, it will likely change to
"scheme" or "schema" in the future.
Signed-off-by: Eric Richter <erichte@linux.ibm.com>
[oliver: added missing SPDX tags, removed unused definitions, style fixes]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
---
V2:
- added secvar device tree node as child of ibm,secureboot
- added version and compatible properties to backend driver struct
- added secvar_ready flag for the API to detect if secvar
initialized successfully
- moved pre-process step to after initial variable load
- moved flags field from secvar struct to secvar node
V3:
- remove the metadata secvar field
- add probe_secvar() to bump compatible flag
- add device tree property for backend-agnostic secure mode setting
- remove backend minor version field
- remove static data allocation in secvar struct
V4:
- add alloc_secvar helpers
- removed ibm,secureboot version bump to v3
- secvars now store their allocated size seperate from the
data size (to permit overallocating)
- split device tree functions into their own file
- device tree changes:
- secvar now a child of ibm,opal
- compatible is "ibm,secvar-v1", backend creates its own node
- secure-mode is now a boolean os-secure-enforcing property
- storage and backends now have their own nodes
V5:
- removed storage device tree subnode
- moved max-var-size to secvar node
- added max-var-key-len
- fixed SPDX header in include/secvar.h
- removed obsolete enum
- removed unused devtree wrappers
- set secvar status prop earlier
V6:
- moved os-secureboot-enforcing to ibm,secureboot
- set secvar compatible based on backend
- removed backend node
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Currently we checksum the read-only parts of skiboot's memory just
before loading and booting petitboot. Commit 9ddc1a6bfaef
("core/util: trap based assertions") modifies the .text after this
point since it needs to disable the trap instructions that we use
to trigger an abort() before entering the kernel.
We can fix this by moving the checksum to after the point where the
traps are patched out. We could do the patching sooner, but since
load_and_boot_kernel() is a fairly complex function it's perferable
to keep boot-time assertion infrastructure active until just before
we enter the kernel.
Reported-by: Carol L Soto <clsoto@us.ibm.com>
Tested-by: Carol L Soto <clsoto@us.ibm.com>
Tested-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Fixes: 9ddc1a6bfaef ("core/util: trap based assertions")
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Right now the romem checksum runs from _start until the start of our
data area. This spans the area used for the MPIPL data structures since
they're included in the SPIRA-H data area.
Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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The ELFv1 branch to NULL catcher puts a function descriptor at 0 which
points to a function that asserts. For ELFv2, put a trap at address 0.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[oliver: commit message prefix]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Using traps for assertions like Linux does gives a few advantages:
- The asm code leading to the failure condition is nicer.
- The interrupt gives a clean snapshot of machine state to dump.
The difficulty with using traps for this in OPAL is that the runtime
component will not deal well with the OS taking the 0x700 interrupt
caused by a trap in OPAL.
The long term goal is to improve the ability of the OS to inspect and
debug OPAL at runtime. For now though, the traps are patched out before
passing control to the OS, and the assert falls through to in-line
failure handling.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[oliver: commit prefix, added and renamed the FWTS label, fix tests]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Sometimes it's useful to fiddle with some of the PCI NVRAM options that
we have. Currently this is mostly for enabling and disabling pci-tracing
mode, but having a common place for this stuff is a good idea.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
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This patch adds support to register for OPAL dump.
- Calculate memory required to capture OPAL dump
- Reserve OPAL dump destination memory
- Add OPAL dump details to MDST and MDDT table
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
[oliver: rebased]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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POWER9P systems have been upgraded with NVLink 3.0 interconnects. The
underlying hardware is fundamentally different--each POWER9 chip has
(1 NPU) * (3 stacks) * (2 bricks) = (6 links)
Where in each POWER9P chip, there are
(3 NPUs) * (4 bricks) = (12 links)
This flatter hierarchy simplifies the firmware implementation a bit, but
also prevents sharing much common code with npu2.
As in previous versions, initialize the hardware and expose each link to
the OS as a virtual PCIe device. This initial support covers NVLink
devices only, with OpenCAPI to follow.
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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When new chip types are added, phys_map_init() will need to know which
memory map it should use.
Instead of directly checking PVR, make it an argument to the function,
so that 'make hw-check' can test all the maps.
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Acked-by: Michael Neuling <mikey@neuling.org>
Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
Acked-by: Stewart Smith <stewart@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Use Software Package Data Exchange (SPDX) to indicate license for each
file that is unique to skiboot.
At the same time, ensure the (C) who and years are correct.
See https://spdx.org/
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
[oliver: Added a few missing files]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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core/init.c:923:28: error: symbol 'main_cpu_entry' redeclared with different type (originally declared at core/init.c:921) - different modifiers
core/init.c:1314:28: error: symbol 'secondary_cpu_entry' redeclared with different type (originally declared at core/init.c:1312) - different modifiers
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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core/init.c:966:1: error: directive in argument list
core/init.c:968:1: error: directive in argument list
core/init.c:970:1: error: directive in argument list
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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version.c:1:12: warning: symbol 'version' was not declared. Should it be static?
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Previously the platform.exit() callback was called before we created the
flattened device tree blob for Linux. Some platforms used this to add
various DT properties and this was broken in commit Fixes: 9fc0c1287ada
("Move FSP specific op-panel calls to platform.exit()") which moved the
exit callback to after the DTB had been created.
The logic for moving the time of the exit call makes some sense since we
want to terminate the IPMI watchdog timer as late as possible, but we
still need a way for the platform modify the DTB as late as possible.
This patch adds another platform callback (yay!) called finalise_dt()
which can be used to graft stuff into the DT.
Suggested-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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We currently have the "pci-eeh-verbose" NVRAM flag that causes phb4 to
print a register dump when it detects the PHB has been fenced. This is
useful for debugging most EEH issues since the kernel may not be ready
to handle EEH events when the problem is first detected.
There's no real reason this needs to be specific to PHB4 so this patch
moves the nvram flag handling into the generic init path (along with the
pcie_max_link_speed flag) so we can add a similar function for PHB3.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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We move the platform exit call much closer to executing the kernel,
which should all be safe, and in fact a much better time to do watchdog
related things.
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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This decouples FSP platform from core skiboot logic by using this small
hack that may/may not be a good idea (although is already used
elsewhere, so at least we're consistent).
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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It's been a good long while since either OPAL POWER7 user touched a
machine, and even longer since they'd have been okay using an old
version rather than tracking master.
There's also been no testing of OPAL on POWER7 systems for an awfully
long time, so it's pretty safe to assume that it's very much bitrotted.
It also saves a whole 14kb of xz compressed payload space.
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Enthusiasticly-Acked-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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Use compiler builtins for the string functions, and compile the
libc/string/ directory with -O2.
This reduces instructions booting skiboot in mambo by 2.9 million in
slow-sim mode, or 3.8 in normal mode, for less than 1kB image size
increase.
This can result in the compiler warning more cases of string function
problems.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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On P9 there are GPIO port 0, 1, 2 for GPIO interrupt, and DIO interrupt
is used to handle the interrupts.
Add support to the DIO interrupts:
1. Add dio_interrupt_register(chip, port, callback) to register the
interrupt;
2. Add dio_interrupt_deregister(chip, port, callback) to deregister;
3. When interrupt on the port occurs, callback is invoked, and the
interrupt status is cleared.
Signed-off-by: Lei YU <mine260309@gmail.com>
[oliver: Fixed Makefile.inc merge conflict]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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Skip the fast reboot checksum, which costs about 4 million cycles
booting skiboot in mambo.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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Most nvram options used by skiboot are just for debug or testing for
regressions. They should never be used long term.
We've hit a number of issues in testing and the field where nvram
options have been set "temporarily" but haven't been properly cleared
after, resulting in crashes or real bugs being masked.
This patch marks most nvram options used by skiboot as dangerous and
prints a chicken to remind users of the problem.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com>
Acked-By: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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On some POWER8 astbmc systems an update to the SBE requires pausing at
runtime to ensure integrity of the SBE. If this is required the BMC will
set a chassis boot option IPMI flag using the OEM parameter 0x62. If
Skiboot sees this flag is set it waits until the SBE update is complete
and the flag is cleared.
Unfortunately the mystery operation that validates the SBE also leaves
it in a bad state and unable to be used for timer operations. To
workaround this the flag is checked as soon as possible (ie. when IPMI
and the console are set up), and once complete the system is rebooted.
Signed-off-by: Samuel Mendoza-Jonas <sam@mendozajonas.com>
Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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When running in virtual memory mode, the radix MMU hid bit should not
be changed, so set this in the initial boot SPR setup.
As a side effect, fast reboot also has HID0:RADIX bit set by the
shared spr init, so no need for an explicit call.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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skiboot.tcl defines PAYLOAD_ADDR as 0x20000000, which is the default in
skiboot. This is also the default in skiboot unless kernel-base-address
is set in the device tree.
If you change PAYLOAD_ADDR to something else for mambo, skiboot won't
see it because it doesn't set that DT property, so fix it so that it does.
Signed-off-by: Russell Currey <ruscur@russell.cc>
Acked-by: Michael Neuling <mikey@neuling.org>
[stewart: fix up mambo hacks for STB]
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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Commit 815417dcda2e ("init, occ: Initialise OCC earlier on BMC systems")
conditionally invoked occ_pstates_init() only on FSP based systems in
load_and_boot_kernel(). Due to this pstate table is re-parsed on FSP
system and skipped on BMC system during fast-reboot. So this patch fixes
this by invoking occ_pstates_init() on all boxes during fast-reboot.
Cc: skiboot-stable@lists.ozlabs.org
Fixes: 815417dcda2e ("init, occ: Initialise OCC earlier on BMC systems")
Reported-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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