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We used bit 4 of `sys_attributes` attribute for MPIPL supported flag.
Unfortunately we forgot to update HDAT spec. Now bit 4 is used for
different purpose. Hence use bit 5 for MPIPL.
Fortunately we don't have any released firmware with MPIPL supported yet.
Hence its safe to make this change.
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Search for different variations of cross-compiler prefixes that might be in
the PATH, in this order of preference:
1. powerpc64-linux-gcc
2. powerpc64le-linux-gcc
3. powerpc64-linux-gnu-gcc
4. powerpc64le-linux-gnu-gcc
The latter two are available as distro packages in at least Debian, Fedora
and Ubuntu.
Tested with GNU Make 3.82 (CentOS 7) and GNU make 4.2.1 (Fedora 30).
Signed-off-by: Thiago Jung Bauermann <bauerman@linux.ibm.com>
Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
Tested-by: Andrew Donnellan <ajd@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Currently, we only have a single range for LPC memory per chip, and we only
allow a single device to use that range.
With upcoming Hostboot/SBE changes, we'll use the chip address extension
mask to give us multiple ranges by using the masked bits of the group ID.
Each device can now allocate a whole 4TB non-mirrored region. We still
don't do >4TB ranges.
If the extension mask is not set correctly, we'll fall back to only
permitting one device and printing an error suggesting a firmware upgrade.
Signed-off-by: Andrew Donnellan <ajd@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Assigning opal IDs to virtual PHBs dynamically may lead to userland
seeing the PCI domain ID for an adapter vary when adding or removing
another adapter (GPU or opencapi).
This patch switches to using static opal IDs for virtual PHBs, based
on their ibm,phb-index property, which was made static by a previous
patch.
Note that the PCI domain IDs will increase on the second chip (or
more, if we had more) because we now reserve 16 IDs per chip for PHBs.
This affects Axone only. We don't change anything on P9 and npu2, to
avoid altering how domain IDs have been shown on already GA'd
platforms.
Reviewed-by: Reza Arbab <arbab@linux.ibm.com>
Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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The 'ibm,phb-index' property of the NPU node is now useless, as we can
have multiple PHBs associated to the same NPU on P9. Let's remove it
to avoid confusion.
Reviewed-by: Reza Arbab <arbab@linux.ibm.com>
Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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On Axone, there's a 1-to-1 mapping between virtual PHBs and NPUs. We
could keep assigning the phb-index of the virtual PHB from the value
found in the npu node of the device tree, but to be consistent with
P9/npu2 and avoid confusion, this patch assigns the phb-index when the
virtual PHB is created, based on the npu index, similarly to what we
do on P9.
Reviewed-by: Reza Arbab <arbab@linux.ibm.com>
Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Until now, opencapi PHBs were not using the 'ibm,phb-index' property,
as it was thought unnecessary. For nvlink, a phb-index was associated
to the npu when parsing hdat data, and the nvlink PHB was reusing the
same value.
It turns out it helps to have the 'ibm,phb-index' property for
opencapi PHBs after all. Otherwise it can lead to wrong results on
platforms like mihawk when trying to match entries in the slot
table. We end up with an opencapi device inheriting wrong properties
in the device tree, because match_slot_phb_entry() default to
phb-index 0 if it cannot find the property. Though it doesn't seem to
cause any harm, it's wrong and a future patch is expected to start
using the slot table for opencapi, so it needs fixing.
The twist is that with opencapi, we can have multiple virtual PHBs for
a single NPU on P9. There's one PHB per (opencapi) brick. Therefore
there's no 1-to-1 mapping between the NPU and PHB index and it no
longer makes sense to associate a phb-index to a npu.
With this patch, opencapi PHBs created under a NPU use a fixed mapping
for their phb-index, based on the brick index. The range of possible
values is 7 to 12. Because there can only be one nvlink PHB per NPU,
it is always using a phb-index of 7.
A side effect is that 2 virtual PHBs on 2 different chips can have the
same phb-index, which is similar to what happens for 'real' PCI PHBs,
but is different from what was happening on a nvlink-only witherspoon
so far.
Reviewed-by: Reza Arbab <arbab@linux.ibm.com>
Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Add a link to the auto-generated github pages documentation and add
instructions for how to build them using Sphinx and some references
on reStructuredText.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Using a normal :: block results in "WARNING: Unexpected indentation." I
don't know why, but replacing it with a plain-text code block cures it.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Apollo was a P7 platform, not P8, and we don't support P7 any more.
VESNIN is a P8 platform. Garrison uses the P8NVL chip, few other minor
mistakes.
There's stilll a bunch of systems missing from here, but eh. I also added
a note about P7 support being dropped.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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This is already included under the "Development Process" and this causes
a warning because there's no doc/CONTRIBUTING.md.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Using all your cores makes re-building the documentation a significantly
faster. It'd be even faster if sphinx would stop assuming every single
.rst file changes between builds, but casual googling didn't reveal a
fix so -EEFFORT. Might be a bug in Sphinx 1.8.3 which Fedora is shipping.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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It was AWOL.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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There's no real point in having a seperate subdir. Move it down a level
and rename it to secvar.rst so Sphinx picks it up automatically.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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A definition for this flag is provided below in a code block. It's not
an OPAL call so there's no ref to it and we get a warning.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Sphinx whines.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Squash another warning
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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This was never implemented and it's documented in the "Future calls"
section.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Squash some warnings.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Sphinx seems to choke if there's an additional indentation in a ::
block.
e.g.:
::
one
two
three
four
It'll complain about the indentation changing at three. A
".. code-block:: text" block doesn't seem to have this problem so use
that instead. Also note that you need a blank line between the
code-block and the start of the actual code block.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
[oliver: cherry picked into master, better late than never]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Sphinx complains about the following line not being indented to the same
starting point as the lines above.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Where the table grid intersect there needs to be a '+' rather than a '|'
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Fixes a few missing ref warnings
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Print the contents of the buffer as an array of bytes in hex, which
avoids endian issues and reading beyond the end of the buffer.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Should be no real code change, these mostly update type declarations
that sparse complains about.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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This fixes quite a few sparse endian annotations across the tree.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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This replaces several instances dt accesses with higher level
primitives throughout the tree.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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This adds support for building LE skiboot with LITTLE_ENDIAN=1.
This is not complete, notably PHB3, NPU* and *CAPI*, but it is
sufficient to build and boot on mambo and OpenPOWER POWER9 systems.
LE/ELFv2 is a nicer calling convention, and results in smaller image and
less stack usage. It also follows the rest of the Linux/OpenPOWER stack
moving to LE.
The OPALv3 call interface still requires an ugly transition through BE
for compatibility, but that is all handled on the OPAL side.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Convert memconsole dt construction and in-memory tables to use
explicit endian conversions.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Convert occ sensors dt construction and in-memory hardware tables to use
explicit endian conversions.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Convert phb4 dt construction and in-memory hardware tables to use
explicit endian conversions.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Convert xive opal calls, dt construction, and in-memory hardware tables
to use explicit endian conversions.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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This requires a small change to flash drivers which assumed 4-byte LPC
reads would not change endian. _raw accessors could be added if this
becomes a signifcant pattern, but for now this hack works.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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This results in the same layout and location of the naca and hv data
structures.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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